TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 75

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Note 1: Output latch register is set to 1.
Note 2: Read-modify-write is prohibited for
Note 3: When port Z is used in input
PZ
(007DH)
PZCR
(007EH)
PZFC
(007FH)
registers PZCR and PZFC.
mode, the PZ register controls the
built-in pull-up resistor.
Read-modify-write is prohibited in
input mode or I/O mode. Setting
the built-in pull-up resistor may be
depended on the states of the
input pin.
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
7
7
7
6
6
6
R
/
<PZ3F>
W
Figure 3.5.14 Register for Port Z
<PZ3C>
,
0
1
SRWE
Port Z Function Register
5
Port Z Control Register
5
5
91C820A-73
setting
Port Z Register
Input
R/W
0
4
4
4
Output
SRWE
0(Output latch register):
1(Output latch register):
Pull-up resistor ON
0: Port
1:
Data form external port
Pull-up resistor OFF
1
0: Input 1: Output
PZ3C
PZ3F
SRWE
R
PZ3
3
3
3
0
0
/
W
(Note 1)
,
W
0: Port
1:
HWR
PZ2C
PZ2F
PZ2
2
2
2
0
0
<PZ0F>
<PZ1F>
PZFC<PZ2F> 1
PZCR<PZ2C> 1
<PZ0>
<PZ1>
HWR
PZ0 (
0
1
PZ1 (
0
1
R/W
W
0: Port
1:
WR
RD
Output
Prohibit this
setting
Output
setting
PZ1F
WR
WR
PZ1
1
1
1
−
1
0
) function setting
) function setting
0
0
0: Port
1:
TMP91C820A
RD
PZ0F
PZ0
0
1
−
0
0
0
2008-02-20
Output
Output
RD
1
1