TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 195

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Internal SCL
output
(TMP91C820A)
SDA line
SCL line
<LRB>
<PIN>
<BB>
(5) Restart
a slave device during transferring data. The following explains how to restart when the
TMP91C820A is in the master mode.
The SDA line remains the high level and the SCL pin is released. Since a stop condition
is not generated on a bus, a bus is assumed to be in a busy state from other devices.
Check the SBI0SR<BB> until it becomes 0 to check that the TMP91C820A is released.
Check the <LRB> until it becomes 1 to check that the SCL line on a bus is not pulled
down to the low level by other devices. After confirming that a bus stays in a free state,
generate a start condition with procedure 3.10.6 (2).
software from the time of restarting to confirm that the bus is free until the time to
generate the start condition.
Restart is used to change the direction of data transfer between a master device and
Clear 0 to the SBI0CR2<MST, TRX, BB>, and set 1 to the <PIN> and release the bus.
In order to meet setup time when restarting, take at least 4.7 µs of waiting time by
Figure 3.10.19 Timing Diagram for TMP91C820A Restart
0 → <MST>
0 → <TRX>
0 → <BB>
1 → <PIN>
9
91C820A-193
1 → <MST>
1 → <TRX>
1 → <BB>
1 → <PIN>
4.7 [ µ s] (Min)
Start codnition
TMP91C820A
2008-02-20