TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 188

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Master
Master
A
B
Internal
SCL output
Internal
SDA output
Internal
SCL output
Internal
SDA output
Accessed to
SBI0DBR or SBI0CR2
<AL>
<MST>
<TRX>
(11) Slave address match detection monitor
(12) GENERAL CALL detection monitor
(13) Last received bit monitor
internal SDA output on the rising edge of the SCL line. If the levels do not match,
arbitration is lost and SBI0SR<AL> is set to 1.
is switched to slave receiver mode. Thus, clock output is stopped in data transfer after
setting <AL> = “1”.
data is written to SBI0CR2.
I2C0AR<ALS> = 0), when a GENERAL CALL is received, or when a slave address
matches the value set in I2C0AR. When I2C0AR<ALS> = 1, SBI0SR<AAS> is set to 1
after the first word of data has been received. SBI0SR<AAS> is cleared to 0 when data
is written to or read from the data buffer register SBI0DBR.
8-bit received data is 0, after a start condition). SBI0SR<AD0> is cleared to 0 when a
start condition or stop condition is detected on the bus.
SBI0SR<LRB>. In the acknowledge mode, immediately after an INTSBI interrupt
request is generated, an acknowledge signal is read by reading the contents of the
SBI0SR<LRB>.
Figure 3.10.12 Example of when TMP91C820A is a Master Device B
The TMP91C820A compares the levels on the bus’s SDA line with those of the
When SBI0SR<AL> is set to 1, SBI0SR<MST, TRX> are cleared to 00 and the mode
SBI0SR<AL> is cleared to 0 when data is written to or read from SBI0DBR or when
SBI0SR<AAS> is set to 1 in slave mode, in address recognition mode (e.g., when
SBI0SR<AD0> is set to 1 in slave mode, when a GENERAL CALL is received (All
The SDA line value stored at the rising edge of the SCL line is set to the
D7A
D7B
1
1
D6A
D6B
2
2
3
3
(D7A = D7B, D6A = D6B)
Keep internal SDA output to high level as losing arbitration
D4A D3A D2A D1A D0A
91C820A-186
4
4
5
Stop the clock pulse
6
7
8
9
D7A’ D6A’ D5A’ D4A’
1
2
TMP91C820A
3
2008-02-20
4