SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 972

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

42.7
Table 42-3.
Note:
972
972
0xC4 - 0xE0
0xEC - 0xF8
0x7C - 0x90
0x98 - 0xAC
Offset
0x0C
0x1C
0x2C
0x3C
0xC0
0xE4
0xE8
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x50
0x54
0x78
0xFC
Analog-to-Digital Converter (ADC) User Interface
If an offset is not listed in the table it must be considered as “reserved”.
...
SAM9X25
SAM9X25
Register Mapping
Register
Control Register
Mode Register
Channel Sequence Register 1
Channel Sequence Register 2
Channel Enable Register
Channel Disable Register
Channel Status Register
Reserved
Last Converted Data Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
Reserved
Reserved
Overrun Status Register
Extended Mode Register
Compare Window Register
Channel Data Register 0
Channel Data Register 1
...
Channel Data Register 11
Reserved
Reserved
Trigger Register
Reserved
Write Protect Mode Register
Write Protect Status Register
Reserved
Reserved
Any offset not listed in
Table 42-3
must be considered as “reserved”.
ADC_SEQR1
ADC_SEQR2
ADC_CDR11
ADC_WPMR
ADC_WPSR
ADC_CHER
ADC_CHDR
ADC_CHSR
ADC_OVER
ADC_TRGR
ADC_LCDR
ADC_CDR0
ADC_CDR1
ADC_CWR
ADC_EMR
ADC_IMR
ADC_IDR
ADC_IER
ADC_ISR
ADC_CR
ADC_MR
Name
...
–
–
–
–
–
–
–
–
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Access
...
–
–
–
–
–
–
–
–
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
...
–
–
–
–
–
–
–
–
–
–
–
–
–