SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 480

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.4.4.3
480
480
Suspension of Transfers Between buffers
SAM9X25
SAM9X25
Ending Multi-buffer Transfers
b u f f e r s i s a f u n c t i o n o f D M A C _ C T R L A x . S R C _ D S C R , D M A C _ C F G x . S R C _ R E P ,
DMAC_CTRLAx.DST_DSCR and DMAC_CFGx.DST_REP registers.
At the end of every buffer transfer, an end of buffer interrupt is asserted if:
Note:
At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
All multi-buffer transfers must end as shown in Row 1 of
every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state,
then the previous buffer transferred was the last buffer and the DMAC transfer is terminated.
F o r r o w s 9 , 1 0 a n d 1 1 o f
DMAC_CTRLBx.AUTO is set), multi-buffer DMAC transfers continue until the automatic mode is
disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit should be programmed to zero in
the end of buffer interrupt service routine that services the next-to-last buffer transfer. This puts
the DMAC into Row 1 state.
For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared) the user must setup the last buffer
d e s c r i p t o r i n m e m o r y s u c h t h a t b o t h L L I . D M A C _ C T R L B x . S R C _ D S C R a n d
LLI.DMAC_CTRLBx.DST_DSCR are one and LLI.DMAC_DSCRx is set to 0.
• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the
• the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.CBTC[n] = ‘1’,
channel number.
when n is the channel number.
The buffer complete interrupt is generated at the completion of the buffer transfer to the
destination.
T a b l e 3 1 - 3 o n p a g e 4 7 9
Table 31-3 on page
, ( D M A C _ D S C R x = 0 a n d
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
479. At the end of