SAM9X25 Atmel Corporation, SAM9X25 Datasheet
SAM9X25
Specifications of SAM9X25
Related parts for SAM9X25
SAM9X25 Summary of contents
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... Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input – Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output • Package – 217-ball BGA, pitch 0.8 mm ® Processor running 400 MHz @ 1.0V +/- 10% AT91SAM ARM-based Embedded MPU SAM9X25 11054A–ATARM–27-Jul-11 ...
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... The External Bus Interface incorporates controllers for 8-bank DDR2/LPDDR, SDRAM/LPS- DRAM, static memories, and specific circuitry for MLC/SLC NAND Flash with integrated ECC. The SAM9X25 is available in a 217-ball BGA package with 0.8mm ball pitch. SAM9X25 2 11054A–ATARM–27-Jul-11 ...
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... Block Diagram Figure 2-1. SAM9X25 Block Diagram 11054A–ATARM–27-Jul-11 PIO PIO SAM9X25 3 ...
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... Fast Interrupt Input PA0-PA31 Parallel IO Controller A PB0-PB18 Parallel IO Controller B PC0-PC31 Parallel IO Controller C PD0-PD21 Parallel IO Controller D SAM9X25 4 gives details on the signal names classified by peripheral. Clocks, Oscillators and PLLs Shutdown, Wakeup Logic ICE and JTAG Reset/Test Debug Unit - DBGU Advanced Interrupt Controller - AIC ...
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... Multimedia Card 0 Slot A Data MCI1_DA0-MCI1_DA3 Multimedia Card 1 Slot A Data 11054A–ATARM–27-Jul-11 External Bus Interface - EBI Static Memory Controller - SMC NAND Flash Support DDR2/SDRAM/LPDDR Controller High Speed MultiMedia Card Interface - HSMCI0-1 SAM9X25 Type Active Level I/O I/O Output Input Low Output Low ...
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... SPI Serial Clock SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-SPIx_NPCS3 SPI Peripheral Chip Select TWDx Two-wire Serial Data TWCKx Two-wire Serial Clock SAM9X25 6 Universal Asynchronous Receiver Transmitter - UARTx Synchronous Serial Controller - SSC Timer/Counter - TCx x=0..5 Serial Peripheral Interface - SPIx Two-Wire Interface -TWIx Type Active Level ...
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... CRSDV Receive Data Valid 11054A–ATARM–27-Jul-11 Pulse Width Modulation Controller- PWMC USB Host High Speed Port - UHPHS USB Device High Speed Port - UDPHS Ethernet 10/100 - EMAC0 RMII Ethernet 10/100 - EMAC1 SAM9X25 Type Active Level Output Analog Analog Analog Analog ...
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... Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference CANRXx CAN input CANTXx CAN output DIBN Soft Modem Signal DIBP Soft Modem Signal SAM9X25 8 Analog-to-Digital Converter - ADC CAN Controller - CANx Soft Modem - SMD Type Active Level Input Input Output I/O Analog Input ...
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... Package and Pinout The SAM9X25 is available in 217-ball BGA package. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. 4.2 I/O Description Table 4-1. I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI EBI_O EBI_CLK RSTJTAG SYSC VBG USBFS USBHS CLOCK DIB 11054A–ATARM–27-Jul-11 shows the orientation of the 217-ball BGA Package. ...
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... Indicates whether the signal is input or output state. • “PU”/”PD” Indicates whether Pull-Up, Pull-Down or nothing is enabled. • “ST” SAM9X25 10 SAM9X25 I/O Type Assignment and Frequency I/O Frequency Charge Load Output (MHz) (pF) Current 40 10 ...
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... The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”. That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address line 20 with Pull-Down. SAM9X25 11 ...
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... PB0 D4 VDDANA GPIO PB1 D2 VDDANA GPIO PB2 E4 VDDANA GPIO PB3 D1 VDDANA GPIO_CLK PB4 E3 VDDANA GPIO PB5 B3 VDDANA GPIO_ANA PB6 C2 VDDANA GPIO_ANA PB7 SAM9X25 12 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O TXD0 I/O RXD0 I/O RTS0 I/O CTS0 I/O SCK0 I/O TXD1 I/O RXD1 I/O TXD2 I/O RXD2 I/O DRXD ...
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... I/O PC2 I/O PC3 I/O PC4 I/O PC5 I/O PC6 I/O PC7 I/O PC8 I/O PC9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O FIQ SAM9X25 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal O O PCK1 O O PCK0 O O PWM0 O O PWM1 O I PWM2 O I PWM3 ADTRG I TWD1 TWCK1 TIOA3 TIOB3 TCLK3 TIOA4 TIOB4 ...
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... POWER VDDPLLA T13 VDDOSC POWER VDDOSC U13 GNDOSC GND GNDOSC H14, K8, VDDCORE POWER VDDCORE K9 H8, J8, GNDCORE GND GNDCORE K10 U16 VDDUTMII POWER VDDUTMII SAM9X25 14 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O NANDOE I/O NANDWE I/O A21/NANDALE I/O A22/NANDCLE I/O NCS3 I/O NWAIT I/O D16 I/O D17 I/O D18 ...
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... BA0 O A17 O BA1 O A18 O BA2 O A19 SDCS O NRD O O NWRE O O NBS1 O SAM9X25 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Reset State Signal, Dir, PU, Dir PD ...
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... RSTJTAG RTCK P10 VDDIOP0 RSTJTAG NRST T11 VDDIOP0 RSTJTAG NTRST A6 VDDBU CLOCK XIN32 A5 VDDBU CLOCK XOUT32 T12 VDDOSC CLOCK XIN U12 VDDOSC CLOCK XOUT SAM9X25 16 Primary Alternate PIO Peripheral A Dir Signal Dir Signal O NBS3/DQM3 I/O I I/O DFSDP ...
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... Power Considerations 5.1 Power Supplies The SAM9X25 has several types of power supply pins. Table 5-1. SAM9X25 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 1.65-3.6V VDDBU 1.65-3.6V VDDUTMIC 0.9-1.1V, 1.0V VDDUTMII 3.0-3.6V, 3.3V VDDPLLA 0.9-1.1V, 1.0V VDDOSC 1.65-3.6V VDDANA 3.0-3.6V, 3.3V Note: 1. Refer to Table 4-2 for more details. 11054A–ATARM–27-Jul-11 ...
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... Memories Figure 6-1. SAM9X25 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 EBI 256 MBytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 256 MBytes DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF 0x3000 0000 EBI 256 MBytes ...
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... Embedded Memories 6.2.1 Internal SRAM The SAM9X25 embeds a total of 32 Kbytes of high-speed SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. 6.2.2 Internal ROM The SAM9X25 embeds an Internal ROM, which contains the SAM-BA program ...
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... SDRAM Power-up Initialization by Software • CAS Latency Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported – Clock Frequency Change in Precharge Power-down Mode Not Supported SAM9X25 20 Average Latency of Transactions) 11054A–ATARM–27-Jul-11 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KBytes. Figure 7-1 on page 22 Figure 6-1 on page 18 peripherals. 11054A–ATARM–27-Jul-11 shows the System Controller block diagram. shows the mapping of the User Interface of the System Controller SAM9X25 21 ...
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... Figure 7-1. SAM9X25 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC 12M RC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset periph_nreset periph_clk[2..3] PA0-PA31 ...
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... Chip ID: 0x819A_05A1 • Chip ID Extension: 4 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 7.2 Backup Section The SAM9X25 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • Real Time Counter (RTC) • Shutdown Controller • 4 Backup Registers • Slow Clock Control Register (SCKCR) • ...
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... SAM9X25 24 Figure 6-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9X25. A peripheral identifier is required Peripheral Identifiers Instance Name Instance Description AIC Advanced Interrupt Controller SYS System Controller Interrupt PIOA,PIOB Parallel I/O Controller A and B ...
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... Peripheral Signal Multiplexing on I/O Lines The SAM9X25 features 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB, PIOC and PIOD. Each line can be assigned to one of three peripheral functions Refer to 11054A– ...
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... SAM9X25 26 11054A–ATARM–27-Jul-11 ...
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... Based on ARM Architecture v5TEJ with Jazelle Technology ® High-performance 32-bit Instruction Set ® High Code Density 16-bit Instruction Set ® 8-bit Instruction Set SAM9X25 SAM9X25 ™ family of general-purpose microproces ...
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... Separate AMBA AHB Buses for Both the 32-bit Data Interface and the 32-bit • Bus Interface Unit – Arbitrates and Schedules AHB Requests – Enables Multi-layer AHB to be Implemented – Increases Overall Bus Bandwidth – Makes System Architecture Mode Flexible SAM9X25 SAM9X25 28 28 Instructions Interface 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
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... Interface ARM9EJ-S Processor Core Read Data Data Instruction Address MMU Instruction Data TLB TLB Data Address AHB Interface and Write Buffer AMBA AHB SAM9X25 SAM9X25 ETM9 Trace Port Interface Instruction Fetches Address ITCM Interface Instruction TCM Instruction Address Instruction Cache 29 29 ...
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... ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. SAM9X25 SAM9X25 30 30 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
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... R10 R10 R11 R11 Interrupt Mode Fast Interrupt Mode R10 R10 R11 R11 SAM9X25 SAM9X25 R8_FIQ R9_FIQ R10_FIQ R11_FIQ 31 31 ...
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... The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC • CPSR SAM9X25 SAM9X25 32 32 Abort Mode Undefined Mode R12 R12 R13_ABORT ...
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... Reserved Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than shows the status register format, where: SAM9X25 SAM9X25 0 Mode Mode bits Thumb state bit FIQ disable IRQ disable 33 33 ...
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... Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while the pipeline, the abort does not take place. SAM9X25 SAM9X25 34 34 into LR (current PC(r15 depending on the exception). ...
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... Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte SAM9X25 SAM9X25 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry RSC Reverse Subtract with Carry ...
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... The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions SAM9X25 SAM9X25 36 36 ARM Instruction Mnemonic List (Continued) Operation Load Register Byte with ...
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... Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch SAM9X25 SAM9X25 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry CMN Compare Negated NEG ...
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... Table 9-5. Register Notes: SAM9X25 SAM9X25 38 38 CP15 Registers Name ( Code (1) 0 Cache type (1) 0 TCM status 1 Control 2 Translation Table Base 3 Domain Access Control 4 Reserved (1) 5 Data fault Status (1) 5 Instruction fault status 6 Fault Address 7 Cache Operations 8 TLB operations (2) 9 cache lockdown ...
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... Symbian OS, WindowsCE, and Linux. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 SAM9X25 SAM9X25 CRn CRm ...
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... When the TLB contains an entry for the MVA (Modi- fied Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. SAM9X25 SAM9X25 40 40 Mapping Details Mapping Size ...
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... Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 SAM9X25 SAM9X25 41 41 ...
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... The Write Buffer can hold words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. SAM9X25 SAM9X25 42 42 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
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... Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 SAM9X25 SAM9X25 43 43 ...
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... The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. SAM9X25 SAM9X25 44 44 Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT that has missed in DCache) • ...
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... Debug and Test 10.1 Description The SAM9X25 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica- tion Channel ...
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... Block Diagram Figure 10-1. Debug and Test Block Diagram TAP: Test Access Port SAM9X25 SAM9X25 46 46 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ARM926EJ-S DMA DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test DTXD DRXD 11054A–ATARM–27-Jul-11 ...
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... Figure 10-2. Application Debug and Trace Environment Example 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 shows a complete debug environment example. The ICE/JTAG interface is used for ICE/JTAG Interface ICE/JTAG Connector RS232 SAM9 Connector SAM9-based Application Board SAM9X25 SAM9X25 Host Debugger Terminal 47 47 ...
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... In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 10-3. Application Test Environment Example SAM9X25 SAM9X25 48 48 shows a test environment example. Test vectors are sent and interpreted by the tes- Test Adaptor ...
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... ICE and JTAG Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select Returned Test Clock JTAG Selection Debug Unit Debug Receive Data Debug Transmit Data SAM9X25 SAM9X25 Type Active Level Input/Output Low Input High Input Low Input Input Output ...
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... TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. SAM9X25 SAM9X25 50 50 ™ is supported via the ICE/JTAG port connected to a 11054A– ...
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... ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant not possible to switch directly between JTAG and ICE operations. A chip reset must be per- formed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 SAM9X25 SAM9X25 51 51 ...
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... VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B2F • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_F03F. SAM9X25 SAM9X25 PART NUMBER ...
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... XTal or external clock frequency detection • attempt to retrieve a valid code from external non-volatile memories (NVM) • execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 (Section 11.1 “ROM Code”) SAM9X25 SAM9X25 53 53 ...
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... MHz external clock or crystal frequency running at 12 MHz is found, then the PLLA is configured to allow communication on the USB link for the SAM-BA Monitor; else the Main Clock is switched to the internal 12 MHz Fast RC, but USB will not be activated. SAM9X25 SAM9X25 54 54 Figure Chip Setup ...
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... BSCR Value. Boot Sequence Register Values NAND SPI0 NPCS0 SDCard Flash SAM9X25 SAM9X25 Figure 11-2 “NVM Bootloader SAM-BA SPI0 NPCS1 TWI EEPROM Monitor ...
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... SPI0 CS0 Flash Boot No SD Card Boot No NAND Flash Boot No SPI0 CS1 Flash Boot No TWI EEPROM Boot No SAM-BA Monitor SAM9X25 SAM9X25 Copy from SPI Flash to SRAM Y es Copy from SD Card to SRAM Y es Copy from NAND Flash to SRAM Y es Copy from ...
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... Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals. Perform the REMAP and set the jump to the downloaded application End SAM9X25 SAM9X25 Restore the reset values for the peripherals and Jump to next boot solution 57 57 ...
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... Figure 11-6. B Opcode Unconditional instruction: 0xE for bits Load PC with PC relative addressing instruction: – 0xF – I==0 (12-bit immediate value) – P==1 (pre-indexed) – U offset added (U==1) or subtracted (U==0) – W==1 SAM9X25 SAM9X25 58 58 0x0000_0000 Internal ROM 0x0010_0000 Internal ROM 0x0030_0000 Internal SRAM 28 27 ...
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... ONFI parameters for ONFI compliant memories. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Size of the code to download in bytes ea000006 B 0x20 eafffffe B 0x04 ea00002f B _main eafffffe B 0x0c eafffffe B 0x10 <- Code size = 4660 bytes 00001234 B 0x14 eafffffe B 0x18 SAM9X25 SAM9X25 ...
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... Figure 11-8. Boot NAND Flash Download SAM9X25 SAM9X25 60 60 Start Initialize NAND Flash interface Send Reset command No First page contains valid header Yes Read NAND Flash and PMECC parameters Read NAND Flash and PMECC parameters from the header Copy the valid code from external NVM to internal SRAM ...
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... If the header is valid, the Boot Program will continue with the detection of valid code. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- eccOffset SAM9X25 SAM9X25 26 25 eccOffset 18 17 sectorSize 10 9 spareSize 2 1 nbSectorPerPage usePmecc ...
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... PMECC base address, pPMERRLOC: pointer to the PMERRLOC base address, PMECC_desc: pointer to the PMECC descriptor, PMECC_status: the status returned by the read of PMECCISR register; SAM9X25 SAM9X25 62 62 Booting on 16-bit NAND Flash is not possible, only 8-bit NAND Flash memories are supported. AT91PS_PMERRLOC pPMERRLOC, ...
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... TT_MAX + 1]; /* polynom order */ short lmu[TT_MAX + 1]; SAM9X25 SAM9X25 63 63 ...
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... SPI DataFlash. It uses only one valid code detection: analysis of ARM exception vectors. The SPI Flash read is done by means of a Continuous Read command from address 0x0. This command is 0xE8 for DataFlash and 0x0B for Serial Flash devices. SAM9X25 SAM9X25 64 64 0x0010_0000 ROM Code ...
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... Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits 2 C-compatible TWI EEPROM memories using 7-bit device contains a list of pins that are driven during the boot program execution. These pins SAM9X25 SAM9X25 Page Size (bytes) Number of Pages 264 512 264 1024 264 2048 264 4096 ...
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... Check if USB Device enumeration has occurred – Check if characters have been received on the DBGU Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in SAM9X25 SAM9X25 66 66 PIO Driven during Boot Program Execution Peripheral ...
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... Address,# write a word Address, Value# read a word Address,# send a file Address,# receive a file Address, NbOfBytes# go Address# display version No argument SAM9X25 SAM9X25 No No Character(s) received on DBGU ? Yes Run monitor Wait for command on the DBGU link Example N# T# O200001,CA# o200001,# H200002,CAFE# ...
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... CRC16 Figure 11-11 SAM9X25 SAM9X25 68 68 There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. ...
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... Windows 98SE to Windows XP Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. SAM9X25 SAM9X25 Device ® . The CDC document, available ...
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... BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. SAM9X25 SAM9X25 70 70 Handled Standard Requests (Continued) Definition Returns status for the specified recipient ...
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... Embedded Characteristics • VDDBU powered • Product-dependent order 12.3 Boot Sequence Controller Registers (BSC) User Interface Table 12-1. Register Mapping Offset Register 0x0 Boot Sequence Configuration Register 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Name BSC_CR SAM9X25 SAM9X25 Access Reset Read-write – ...
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... Factory Value:0x0000_0000 • BOOTx: Boot media sequence Is defined in the product-dependent ROM code. • BOOTKEY 0xB5 (VALID): valid boot key To avoid spurious writing, this key is necessary for write accesses. SAM9X25 SAM9X25 BOOTKEY BOOT BOOT ...
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... Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the • General Interrupt Mask – Provides Processor Synchronization on Events Without Triggering an Interrupt • Write Protected Registers 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 External Interrupts External Sources Enabled Processor SAM9X25 SAM9X25 ® Processor 73 73 ...
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... Block Diagram Figure 13-1. Block Diagram 13.4 Application Block Diagram Figure 13-2. Description of the Application Block 13.5 AIC Detailed Block Diagram Figure 13-3. AIC Detailed Block Diagram SAM9X25 SAM9X25 74 74 FIQ IRQ0-IRQn Embedded PeripheralEE Embedded Peripheral Embedded Peripheral Standalone OS Drivers Applications General OS Interrupt Handler Advanced Interrupt Controller ...
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... FIQ, SYS, and PID2 to PID31. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 I/O Line Description Pin Description Fast Interrupt Interrupt 0 - Interrupt n I/O Lines Signal AIC FIQ AIC IRQ SAM9X25 SAM9X25 Type Input Input I/O Line Peripheral PC31 A PB18 ...
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... The AIC_ISR register reads the number of the current interrupt (see 79) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. SAM9X25 SAM9X25 76 76 (See “Priority Controller” on page 79.) The automatic clear reduces See “ ...
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... AIC_SMRI (SRCTYPE) Level/ AIC_IPR Edge Edge Detector Set Clear AIC_SMRi SRCTYPE Level/ AIC_IPR Edge Pos./Neg. Edge Detector Clear AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR FF AIC_IDCR AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR FF AIC_IDCR SAM9X25 SAM9X25 77 77 ...
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... For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. Figure 13-6. Figure 13-7. SAM9X25 SAM9X25 78 78 External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) ...
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... Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active SAM9X25 SAM9X25 79 79 ...
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... This section gives an overview of the fast interrupt handling sequence when using the AIC assumed that the programmer understands the architecture of the ARM processor, and espe- cially the processor interrupt modes and the associated status bits assumed that: SAM9X25 SAM9X25 80 80 PC,[PC,# -&F20] 11054A–ATARM–27-Jul-11 ...
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... If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared dur- ing this phase. The “I” bit in SPSR is significant set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked). SAM9X25 SAM9X25 81 81 ...
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... The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati- SAM9X25 SAM9X25 82 82 PC,[PC,# -&F20] 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
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... The “F” bit in SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). SAM9X25 SAM9X25 83 83 ...
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... AIC_ISR. Extra AIC_IVR reads perform the same operations. However recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. SAM9X25 SAM9X25 84 84 AIC_IPR Input Stage ...
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... Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt strongly recommended to use this mask with caution. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 SAM9X25 SAM9X25 85 85 ...
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... Source Vector Register” on page 89 • “AIC Spurious Interrupt Vector Register” on page 100 • “AIC Debug Control Register” on page 101 SAM9X25 SAM9X25 86 86 (AIC_WPSR) is set and the WPVSRC field indicates in which register AIC Write Protect Mode Register AIC Write 11054A– ...
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... Spurious Interrupt Vector Register Debug Control Register Reserved (2) Fast Forcing Enable Register (2) Fast Forcing Disable Register (2) Fast Forcing Status Register Reserved Write Protect Mode Register Write Protect Status Register Reserved SAM9X25 SAM9X25 Name Access Reset AIC_SMR0 Read-write AIC_SMR1 Read-write --- --- AIC_SMR31 Read-write AIC_SVR0 Read-write ...
Page 88
... The priority level is not used for the FIQ in the related SMR register AIC_SMRx. • SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources. Value Name 0x0 INT_LEVEL_SENSITIVE 0x1 INT_EDGE_TRIGGERED 0x2 EXT_HIGH_LEVEL 0x3 EXT_POSITIVE_EDGE SAM9X25 SAM9X25 – – – – – ...
Page 89
... The user may store in these registers the addresses of the corresponding handler for each interrupt source. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- VECTOR VECTOR VECTOR VECTOR AIC Write Protect Mode Register SAM9X25 SAM9X25 ...
Page 90
... The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. SAM9X25 SAM9X25 ...
Page 91
... The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- FIQV FIQV FIQV FIQV SAM9X25 SAM9X25 ...
Page 92
... IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. SAM9X25 SAM9X25 – – – – – – – – ...
Page 93
... PID5 PID4 PID3 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9X25 SAM9X25 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS FIQ PID26 PID25 ...
Page 94
... NFIQ: NFIQ Status 0 = nFIQ line is deactivated nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated nIRQ line is active. SAM9X25 SAM9X25 – – – – – – – ...
Page 95
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9X25 SAM9X25 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS FIQ 95 95 ...
Page 96
... Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Disable effect Disables corresponding interrupt. SAM9X25 SAM9X25 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 4 ...
Page 97
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9X25 SAM9X25 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS FIQ 97 97 ...
Page 98
... Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Set effect Sets corresponding interrupt. SAM9X25 SAM9X25 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 4 ...
Page 99
... SAM9X25 SAM9X25 – – – – – – – – – – – – ...
Page 100
... This register can only be written if the WPEN bit is cleared in • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. SAM9X25 SAM9X25 100 100 29 28 ...
Page 101
... AIC Write Protect Mode Register SAM9X25 SAM9X25 – – – – – – – – – – GMSK PROT 101 101 ...
Page 102
... PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Enable effect Enables the fast forcing feature on the corresponding interrupt. SAM9X25 SAM9X25 102 102 PID29 PID28 PID27 PID21 PID20 PID19 PID13 ...
Page 103
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9X25 SAM9X25 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS – 103 103 ...
Page 104
... PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt The Fast Forcing feature is enabled on the corresponding interrupt. SAM9X25 SAM9X25 104 104 PID29 PID28 PID27 PID21 PID20 ...
Page 105
... Should be written at value 0x414943 ("AIC" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- WPKEY WPKEY WPKEY — — — SAM9X25 SAM9X25 — — WPEN 105 105 ...
Page 106
... WPVSRC. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading AIC_WPSR automatically clears all fields. SAM9X25 SAM9X25 106 106 — ...
Page 107
... Either General Reset, Wake-up Reset, Software Reset, User Reset, Watchdog • External Reset Signal Shaping • AMBA – Interfaces to the ARM 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Reset ™ -compliant Interface ® Advanced Peripheral Bus SAM9X25 SAM9X25 107 107 ...
Page 108
... Crystal Oscil- lator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con- troller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. SAM9X25 SAM9X25 108 108 Reset Controller POR ...
Page 109
... Figure 14-2 shows the block diagram of the NRST Manager. RSTC_SR URSTS NRSTL NRST RSTC_MR nrst_out External Reset Timer Slow Clock cycles. This gives the approximate duration of an assertion between 60 μs SAM9X25 SAM9X25 user_reset ERSTL exter_nreset 109 109 ...
Page 110
... Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 14-4 SAM9X25 SAM9X25 110 110 XXX BMS sampling delay = 3 cycles shows how the General Reset affects the reset signals ...
Page 111
... When the Main Supply is detected falling, the reset signals are immediately asserted. This tran- sition is synchronous with the output of the Main Supply POR. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Startup Time Processor Startup XXX EXTERNAL RESET LENGTH BMS Sampling = 2 cycles SAM9X25 SAM9X25 Any Freq. 0x0 = General Reset XXX 111 111 ...
Page 112
... EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How- ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. SAM9X25 SAM9X25 112 112 Resynch. Processor Startup 2 cycles ...
Page 113
... If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH SAM9X25 SAM9X25 Processor Startup 0x4 = User Reset 113 113 ...
Page 114
... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. SAM9X25 SAM9X25 114 114 Resynch. Processor Startup ...
Page 115
... The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Any Freq. Processor Startup = 3 cycles Any XXX proc_nreset signal. SAM9X25 SAM9X25 0x2 = Watchdog Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 115 115 ...
Page 116
... Reading the RSTC_SR status register resets the URSTS bit . Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) SAM9X25 SAM9X25 116 116 read RSTC_SR 2 cycle resynchronization 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Figure ...
Page 117
... The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write SAM9X25 SAM9X25 Reset Back-up Reset - 0x0000_0001 0x0000_0000 - 0x0000_0000 117 117 ...
Page 118
... If KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9X25 SAM9X25 118 118 KEY ...
Page 119
... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. SAM9X25 SAM9X25 119 119 – ...
Page 120
... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 μs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9X25 SAM9X25 120 120 29 28 ...
Page 121
... Time, Date and Alarm 32-bit Parallel Load 15.3 Block Diagram Figure 15-1. RTC Block Diagram Slow Clock: SLCK Bus Interface 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 32768 Divider Time Bus Interface Entry Control SAM9X25 SAM9X25 Date Interrupt RTC Interrupt Control 121 121 ...
Page 122
... Each of these fields can be enabled or disabled to match the alarm condition: • If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled given month, date, hour/minute/second. SAM9X25 SAM9X25 122 122 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
Page 123
... If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be pro- grammed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked. SAM9X25 SAM9X25 123 123 ...
Page 124
... Figure 15-2. Update Sequence SAM9X25 SAM9X25 124 124 Begin Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR No ACKUPD = 1 ? Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End Polling or IRQ (if enabled) 11054A– ...
Page 125
... RTC_CALR Read-write RTC_TIMALR Read-write RTC_CALALR Read-write RTC_SR Read-only RTC_SCCR Write-only RTC_IER Write-only RTC_IDR Write-only RTC_IMR Read-only RTC_VER Read-only – – – – SAM9X25 SAM9X25 Reset 0x0 0x0 0x0 0x01210720 0x0 0x01010000 0x0 – – – 0x0 0x0 – – 125 125 ...
Page 126
... The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) 3 – SAM9X25 SAM9X25 126 126 – – – – – – 13 ...
Page 127
... SAM9X25 SAM9X25 – – – – – – – – – – – HRMOD 127 127 ...
Page 128
... HOUR: Current Hour The range that can be set (BCD) in 12-hour mode (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode AM PM. All non-significant bits read zero. SAM9X25 SAM9X25 128 128 – – ...
Page 129
... The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- YEAR CENT SAM9X25 SAM9X25 26 25 DATE 18 17 MONTH 129 129 ...
Page 130
... This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled The hour-matching alarm is enabled. SAM9X25 SAM9X25 130 130 – ...
Page 131
... The date-matching alarm is enabled. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- – – – – – – – SAM9X25 SAM9X25 26 25 DATE 18 17 MONTH 10 9 – – – – – 0 – 131 131 ...
Page 132
... No calendar event has occurred since the last clear least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. SAM9X25 SAM9X25 132 132 – ...
Page 133
... CALCLR TIMCLR SAM9X25 SAM9X25 26 25 – – – – – – SECCLR ALRCLR ACKCLR 24 – 16 – 8 – 0 133 133 ...
Page 134
... The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable effect The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable effect. • The selected calendar event interrupt is enabled. SAM9X25 SAM9X25 134 134 – – ...
Page 135
... CALDIS TIMDIS SAM9X25 SAM9X25 – – – – – – SECDIS ALRDIS ACKDIS – – 8 – 0 135 135 ...
Page 136
... TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled The selected calendar event interrupt is enabled. SAM9X25 SAM9X25 136 136 – ...
Page 137
... NVCALALR SAM9X25 SAM9X25 26 25 – – – – – – NVTIMALR NVCAL NVTIM 24 – 16 – 8 – 0 137 137 ...
Page 138
... SAM9X25 SAM9X25 138 138 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
Page 139
... CPIV 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ® ® /WinCE compliant tick generator ™ -compliant Interface PIT_MR PIV = 0 1 PIT_PIVR PIT_PIIR SAM9X25 SAM9X25 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR PICNT PICNT PIT_MR PITIEN pit_irq 139 139 ...
Page 140
... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. SAM9X25 SAM9X25 140 140 Figure 16-2 illustrates 11054A– ...
Page 141
... Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 0 SAM9X25 SAM9X25 1 141 141 ...
Page 142
... Periodic Interval Timer (PIT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register SAM9X25 SAM9X25 142 142 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset ...
Page 143
... The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- – – – – – PIV PIV SAM9X25 SAM9X25 – PITIEN PITEN PIV 143 143 ...
Page 144
... SAM9X25 SAM9X25 – – – – – – – – – – – PITS 144 144 ...
Page 145
... PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- PICNT CPIV CPIV SAM9X25 SAM9X25 CPIV 145 145 ...
Page 146
... PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAM9X25 SAM9X25 146 146 PICNT ...
Page 147
... Interface ® Advanced Peripheral Bus WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset SAM9X25 SAM9X25 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 147 147 ...
Page 148
... If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. SAM9X25 SAM9X25 148 148 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
Page 149
... WDIDLEHLT and WDDBGHLT in the WDT_MR. Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Watchdog Error WDT_CR = WDRSTT SAM9X25 SAM9X25 Watchdog Underflow if WDRSTEN WDRSTEN is 0 149 149 ...
Page 150
... Watchdog Timer (WDT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register SAM9X25 SAM9X25 150 150 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
Page 151
... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- KEY – – – – – – – – – SAM9X25 SAM9X25 – – – – – – – – WDRSTT 151 151 ...
Page 152
... The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable SAM9X25 SAM9X25 152 152 ...
Page 153
... Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 SAM9X25 SAM9X25 153 153 ...
Page 154
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. SAM9X25 SAM9X25 154 154 – ...
Page 155
... SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset SHDW_MR RTTWK SHDW_SR set read SHDW_SR reset SHDW_MR RTCWK SHDW_SR set SAM9X25 SAM9X25 SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW 155 155 ...
Page 156
... The software is able to control the pin (SHDW_CR) with the bit SHDW at 1. The shutdown is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is password-protected and so the value written SAM9X25 SAM9X25 156 156 read SHDW_SR reset ...
Page 157
... RTC alarm status flag is cleared before shutting down the system.Otherwise, no rising edge of the status flag may be detected and the wake-up fails fail. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 pin is released new input change is detected before the counter reaches the corre- SAM9X25 SAM9X25 157 157 ...
Page 158
... Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register SAM9X25 SAM9X25 158 158 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0003 0x0000_0000 11054A–ATARM–27-Jul-11 ...
Page 159
... KEY – – – – – – – – – pin. SAM9X25 SAM9X25 – – – – – – – – SHDW 159 159 ...
Page 160
... Because of the internal synchronization of WKUP0, the (CPTWK Slow Clock cycles after the event on WKUP. • RTCWKEN: Real-time Clock Wake-up Enable 0 = The RTC Alarm signal has no effect on the Shutdown Controller The RTC Alarm signal forces the de-assertion of the SAM9X25 SAM9X25 160 160 – ...
Page 161
... At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. • RTCWK: Real-time Clock Wake- wake-up alarm from the RTC occurred since the last read of SHDW_SR least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. SAM9X25 SAM9X25 161 161 – ...
Page 162
... SAM9X25 SAM9X25 162 162 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
Page 163
... General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset Register 0x0 General Purpose Backup Register 0 ... ... 0xc General Purpose Backup Register 3 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Name SYS_GPBR0 ... SYS_GPBR3 SAM9X25 SAM9X25 Access Reset Read-write – ... ... Read-write – 163 163 ...
Page 164
... General Purpose Backup Register x Name: SYS_GPBRx Address: 0xFFFFFE60 [0], 0xFFFFFE64 [1], 0xFFFFFE68 [2], 0xFFFFFE6C [3] Access: Read-write • GPBR_VALUEx: Value of GPBR x SAM9X25 SAM9X25 164 164 GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx 11054A–ATARM–27-Jul-11 ...
Page 165
... Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller. • Enable the 32,768 Hz oscillator by setting the bit OSC32EN to 1. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 On Chip RC OSC Slow Clock XIN32 Oscillator XOUT32 SAM9X25 SAM9X25 RCEN Slow Clock SLCK OSCSEL OSC32EN OSC32BYP 165 165 ...
Page 166
... Switch from 32,768 Hz oscillator to internal RC by setting the bit OSCSEL to 0. • Wait 5 slow clock cycles for internal resynchronization. • Disable the 32,768 Hz oscillator by setting the bit OSC32EN to 0. SAM9X25 SAM9X25 166 166 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
Page 167
... Slow Clock Configuration (SCKC) User Interface Table 20-1. Register Mapping Offset Register 0x0 Slow Clock Configuration Register 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Name Access SCKC_CR Read-write SAM9X25 SAM9X25 Reset 0x0000_0001 167 167 ...
Page 168
... OSCSEL SAM9X25 SAM9X25 26 25 – – – – – – OSC32BYP OSC32EN RCEN 24 – 16 – 8 – 0 168 168 ...
Page 169
... PLLACK is the output of the Divider and 400 to 800 MHz programmable PLL (PLLA) • UPLLCK is the output of the 480 MHz UTMI PLL (UPLL) 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Section 22.13 ”Power Management Controller (PMC) User SAM9X25 SAM9X25 Interface”. However, 169 169 ...
Page 170
... OSC32BYP to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32,768 Hz oscillator can be enabled by setting to 1, respectively, RCEN bit and OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source. SAM9X25 SAM9X25 170 170 Clock Generator On Chip ...
Page 171
... Enable the bypass path OSC32BYP bit set to 1. • Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Clock Generator On Chip RC OSC Slow Clock XIN32 Oscillator XOUT32 SAM9X25 SAM9X25 RCEN Slow Clock SLCK OSCSEL OSC32EN OSC32BYP 171 171 ...
Page 172
... Switch from 32768 Hz oscillator to internal RC by setting the bit OSCSEL to 0. • Wait 5 slow clock cycles for internal resynchronization. • Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0. • Switch the master clock back to the slow clock domain SAM9X25 SAM9X25 172 172 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
Page 173
... OSCSEL SAM9X25 SAM9X25 26 25 – – – – – – OSC32BYP OSC32EN RCEN 24 – 16 – 8 – 0 173 173 ...
Page 174
... MHz RC oscillator. This fast RC oscillator allows the processor to start or restart in a few microseconds when 12 MHz internal RC is selected. The 12 MHz crystal oscillator can be bypassed by setting the bit MOSCXTBY to accept an exter- nal main clock on XIN. SAM9X25 SAM9X25 174 174 MOSCRCEN MOSCRCF ...
Page 175
... Crystal Startup Time Wait MOSCRCS = 1 System switches on Main Clock to speed-up the boot System is running at 12 MHz External oscillator is started for better accuracy MOSCXTEN = 1 MOSCSEL = 0 SAM9X25 SAM9X25 MOSCRCEN Main Clock MOSCSEL MOSCXTEN MOSCXTBY Wait MOSCXTS = 1 User switches on external oscillator MOSCSEL=1 Wait while MOSCSELS =1 ...
Page 176
... Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. 21.6 MHz Crystal Oscillator After reset, the MHz Crystal Oscillator is disabled and it is not selected as the source of MAINCK. SAM9X25 SAM9X25 176 176 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
Page 177
... Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 SAM9X25 SAM9X25 177 177 ...
Page 178
... MAINCK, the 12 MHz frequency must also be selected because the UTMI PLL multiplier contains a built-in multiplier obtain the USB High Speed 480 MHz MHz crystal is needed to use the USB. SAM9X25 SAM9X25 178 178 shows the block diagram of the divider and PLLA block. DIVA ...
Page 179
... The user has to load the number of Slow Clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 UPLLEN MAINCK UTMI PLL UPLLCOUNT UTMI PLL SLCK Counter SAM9X25 SAM9X25 UPLLCK LOCKU 179 179 ...
Page 180
... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery SAM9X25 SAM9X25 180 180 DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK). ...
Page 181
... Figure 22-1. Master Clock Controller MAINCK PLLACK UPLLCK 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 PMC_MCKR PMC_MCKR CSS SLCK Master Clock Prescaler PRES MCK To the Processor Clock Controller (PCK) SAM9X25 SAM9X25 181 181 ...
Page 182
... Note: When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. SAM9X25 SAM9X25 182 182 USBS USBDIV ...
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... In order to save power consumption, the division factor can PMC_PCR is a regis- ter that features a command and acts like a mailbox. To write the division factor on a particular peripheral, the user needs to write a WRITE command, the peripheral ID and the chosen divi- 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 SAM9X25 SAM9X25 183 183 ...
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... PMC_SR register to be set. This can be done either by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register. SAM9X25 SAM9X25 184 184 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 ...
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... The Master Clock and the Processor Clock are configurable via the PMC_MCKR register. The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By default, the selected clock source is slow clock. 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 write_register(CKGR_PLLAR,0x00040805) SAM9X25 SAM9X25 185 185 ...
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... Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) SAM9X25 SAM9X25 186 186 IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCK goes high and MCKRDY is set. ...
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... Depending on the system used, 19 peripheral clocks can be enabled or disabled. The PMC_PCR provides a clear view as to which peripheral clock is enabled. Note: Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Each enabled peripheral clock corresponds to Master Clock. SAM9X25 SAM9X25 187 187 ...
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... Table 22-1. To Main Clock SLCK PLL Clock Notes: Table 22-2. To PLLA Clock UPLL Clock SAM9X25 SAM9X25 188 188 and Table 22-2 give the worst case timings required for the Master Clock to switch Clock Switching Timings (Worst Case) From Main Clock – 0.5 x Main Clock + 4.5 x SLCK ...
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... Figure 22-3. Switch Master Clock from Slow Clock to PLL Clock Write PMC_MCKR Figure 22-4. Switch Master Clock from Main Clock to Slow Clock Write PMC_MCKR 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul-11 Slow Clock PLL Clock LOCK MCKRDY Master Clock Slow Clock Main Clock MCKRDY Master Clock SAM9X25 SAM9X25 189 189 ...
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... Figure 22-5. Change PLLA Programming Write CKGR_PLLAR Figure 22-6. Programmable Clock Output Programming Write PMC_PCKx Write PMC_SCER Write PMC_SCDR SAM9X25 SAM9X25 190 190 Slow Clock PLLA Clock LOCKA MCKRDY Master Clock PLL Clock PCKRDY PCKx Output PLL Clock is selected Slow Clock PCKx is enabled PCKx is disabled 11054A– ...
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... PMC_IER Write-only PMC_IDR Write-only PMC_SR Read-only PMC_IMR Read-only – – PMC_PLLICPR Write-only – – PMC_WPMR Read-write PMC_WPSR Read-only – – PMC_PCR Read-write SAM9X25 SAM9X25 Reset N.A. N.A. 0x0000_0005 N.A. – 0x0000_0000 – 0x1020_0000 0x0100_0008 0x0000_0000 0x0000_3F00 – 0x0000_0001 – 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 – N.A. N.A. ...
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... Enables the UHP48M and UHP12M OHCI clocks. • UDP: USB Device Clock Enable effect Enables the USB Device clock. • PCKx: Programmable Clock x Output Enable effect Enables the corresponding Programmable Clock output. SAM9X25 SAM9X25 192 192 – – ...
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... SMDCK – SAM9X25 SAM9X25 – – – – – PCK1 PCK0 2 1 DDRCK – PCK – – 193 193 ...
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... UDP: USB Device Port Clock Status 0 = The USB Device clock is disabled The USB Device clock is enabled. • PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled The corresponding Programmable Clock output is enabled. SAM9X25 SAM9X25 194 194 – ...
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... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9X25 SAM9X25 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 - - 195 195 ...
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... PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Disable effect Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. SAM9X25 SAM9X25 196 196 PID29 PID28 PID27 PID21 ...
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... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9X25 SAM9X25 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 – – 197 197 ...
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... Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time. • BIASEN: UTMI BIAS Enable 0 = The UTMI BIAS is disabled The UTMI BIAS is enabled. • BIASCOUNT: UTMI BIAS Start-up Time Specifies the number of Slow Clock cycles for the UTMI BIAS start-up time. SAM9X25 SAM9X25 198 198 – ...
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... CFDEN: Clock Failure Detector Enable 11054A–ATARM–27-Jul-11 11054A–ATARM–27-Jul- – – – KEY MOSCXTST – – MOSCRCEN SAM9X25 SAM9X25 – CFDEN MOSCSEL – MOSCXTBY MOSCXTEN 199 199 ...
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... MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINFRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled The Main Oscillator has been enabled previously and MAINF value is available. SAM9X25 SAM9X25 200 200 – ...