SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 438

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 30-15. Burst Read Access, Latency = 3, DDR2-SDRAM Devices
Figure 30-16. Burst Read Access, Latency = 2, SDR-SDRAM Devices
30.5.3
438
438
COMMAND
COMMAND
DQS[1:0]
DQS[1:0]
DM[3:0]
SDCLK
BA[1:0]
DM[1:0]
D[31:0]
A[12:0]
SDCLK
BA[1:0]
D[15:0]
A[12:0]
SAM9X25
SAM9X25
Refresh (Auto-refresh Command)
NOP
0
NOP
0
3
col a
READ
An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated
internally by the SDRAM device and incremented after each auto-refresh automatically. The
DDRSDRC generates these auto-refresh commands periodically. A timer is loaded with the
value in the register DDRSDRC_TR that indicates the number of clock cycles between refresh
cycles. When the DDRSDRC initiates a refresh of an SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM device, the slave indicates that
the device is busy. A request of refresh does not interrupt a burst transfer in progress.
Col a
READ
F
Latency = 2
NOP
Latency = 3
NOP
DaDb
DcDd
Da
DeDf
Db
BST
Dc
Dd
Dg Dh
De
NOP
Df
Dg
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Dh