SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 444

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.5.4.4
30.5.5
Figure 30-24. Trp and Trcd Timings
444
444
COMMAND
SAM9X25
SAM9X25
Multi-port Functionality
DQS[1:0]
SDCLK
BA[1:0]
DM1:0]
D[15:0]
A[12:0]
Reset Mode
NOP
0
3
The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-
power command bits (LPCB) to 11 and the clock frozen command bit (CLK_FR) to 1.
When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the control-
ler is frozen. Before enabling this mode, the end user must assume there is not an access in
progress.
To exit reset mode, the low-power command bits (LPCB) must be set to “00”, clock frozen com-
mand bit (CLK_FR) set to 0 and an initialization sequence must be generated by software. See
Section 30.4.3 “DDR2-SDRAM Initialization” on page
The SDRAM protocol imposes a check of timings prior to performing a read or a write access,
thus decreasing the performance of systems. An access to SDRAM is performed if banks and
rows are open (or active). To activate a row in a particular bank, it has to de-active the last open
row and open the new row. Two SDRAM commands must be performed to open a bank: Pre-
charge and Active command with respect to Trp timing. Before performing a read or write
command, Trcd timing must checked.
This operation represents a significative loss. (see
The multi-port controller has been designed to mask these timings and thus improve the band-
width of the system.
DDRSDRC is a multi-port controller since four masters can simultaneously reach the controller.
This feature improves the bandwidth of the system because it can detect four requests on the
AHB slave inputs and thus anticipate the commands that follow, PRECHARGE and ACTIVE
commands in bank X during current access in bank Y. This allows Trp and Trcd timings to be
masked (see
were already open. The best condition is met when the four masters work in different banks. In
PRCHG
NOP
Trp
4 cycles before performing a read command
Figure
ACT
30-25). In the best case, all accesses are done as if the banks and rows
NOP
Trcd
READ
BST
Latency =2
Figure
426.
NOP
30-24).
Da Db
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11