SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 676

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

35.7.4
676
676
SAM9X25
SAM9X25
SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed
following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the
SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no
effect when the SPI is programmed in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
(For more information on BITS field, see also, the
“SPI Chip Select Register” on page
When all the bits are processed, the received data is transferred in the Receive Data Register
and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new
data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data
is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data
has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred.
If no data has been received since the last reset, all bits are transmitted low, as the Shift Regis-
ter resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the
TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls
and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in
SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent
updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no
character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last
load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received
character is retransmitted.
Figure 35-11
Figure 35-11. Slave Mode Functional Bloc Diagram
SPCK
MOSI
NSS
shows a block diagram of the SPI when operating in Slave Mode.
SPIDIS
SPIEN
SPIENS
SPI_CSR0
LSB
NCPHA
CPOL
BITS
688.)
Shift Register
Clock
SPI
SPI_RDR
SPI_TDR
(Note:)
below the register table;
RD
TD
MSB
OVRES
RDRF
TDRE
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Section 35.8.9
MISO