SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 1012

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SAM9X25

Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9X25

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
44.8.1
1012
1012
SAM9X25
SAM9X25
Write Protection Registers
To prevent any single software error that may corrupt SSC behavior, certain address spaces can
be write-protected by setting the WPEN bit in the
(SSC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Pro-
tect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
“SSC Clock Mode Register” on page 1015
“SSC Receive Clock Mode Register” on page 1016
“SSC Receive Frame Mode Register” on page 1018
“SSC Transmit Clock Mode Register” on page 1020
“SSC Transmit Frame Mode Register” on page 1022
“SSC Receive Compare 0 Register” on page 1027
“SSC Receive Compare 1 Register” on page 1028
“SSC Write Protect Mode Register”
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11

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