SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 917

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.7.4.3
41.7.5
41.7.5.1
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Error Interrupt Handler
Low-power Mode
Overload
Enabling Low-power Mode
When one of the error counters values exceeds 96, an increased error rate is indicated to the
controller through the WARN bit in CAN_SR register, but the node remains error active. The cor-
responding interrupt is pending while the interrupt is set in the CAN_IMR register.
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
ERRA, WARN, ERRP and BOFF (CAN_SR) store the key transitions of the CAN bus status as
defined in
values as described in
These flags are latched to keep from triggering a spurious interrupt in case these bits are used
as the source of an interrupt. Thus, these flags may not reflect the current status of the CAN bus.
The current CAN bus state can be determined by reading the TEC and REC fields of CAN_ECR.
The overload frame is provided to request a delay of the next data or remote frame by the
receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive over-
load frame”) related to the intermission field respectively.
Reactive overload frames are transmitted after detection of the following error conditions:
The CAN controller can generate a request overload frame automatically after each message
sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the
CAN_MR register.
Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in
the CAN_MR register is not set. An overload flag is generated in the same way as an error flag,
but error counters do not increment.
In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are
inactive.
In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP
signal in the CAN_SR register is set. These two fields are exclusive except after a CAN control-
ler reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Low-
power Mode is disabled and the WAKEUP bit is set in the CAN_SR register only after detection
of 11 consecutive recessive bits on the bus.
A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR
global register. The CAN controller enters Low-power Mode once all pending transmit messages
are sent.
When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is
set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated
while SLEEP is set.
• Detection of a dominant bit during the first two bits of the intermission field
• Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit
by a receiver or a transmitter at the last bit of an error or overload frame delimiter
Figure 41-7 on page
Section “Fault Confinement” on page
916. The transitions depend on the TEC and REC (CAN_ECR)
916.
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