SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 969

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

42.6.5
42.6.6
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Conversion Triggers
Sleep Mode and Conversion Sequencer
Conversions of the active analog channels are started with a software or hardware trigger. The
software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1.
The hardware trigger can be selected by the TRGMOD field in the
between:
The minimum time between 2 consecutive trigger events must be strictly greater than the dura-
tion time of the longest conversion sequence according to configuration of registers ADC_MR,
ADC_CHSR, ADC_SEQR1, ADC_SEQR2.
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at
each rising edge of the selected signal. Due to asynchronous handling, the delay may vary in a
range of 2 MCK clock periods to 1 ADC clock period.
Only one start command is necessary to initiate a conversion sequence on all the channels. The
ADC hardware logic automatically performs the conversions on the active channels, then waits
for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Reg-
isters permit the analog channels to be enabled or disabled independently.
If the ADC is used with a DMA, only the transfers of converted data from enabled channels are
performed and the resulting data buffers should be interpreted accordingly.
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is
not being used for conversions. Sleep Mode is selected by setting the SLEEP bit in the Mode
Register ADC_MR.
The Sleep mode is automatically managed by a conversion sequencer, which can automatically
process the conversions of all channels at lowest power consumption.
This mode can be used when the minimum period of time between 2 successive trigger events
is greater than the startup period of Analog-Digital converter (See the product ADC Characteris-
tics section).
When a start conversion request occurs, the ADC is automatically activated. As the analog cell
requires a start-up time, the logic waits during this time and starts the conversion on the enabled
channels. When all conversions are complete, the ADC is deactivated until the next trigger. Trig-
gers occurring during the sequence are not taken into account.
The conversion sequencer allows automatic processing with minimum processor intervention
and optimized power consumption. Conversion sequences can be performed periodically using
the internal timer (ADC_TRGR register). The periodic acquisition of several samples can be pro-
cessed automatically without any intervention of the processor thanks to the DMA.
• any edge, either rising or falling or both, detected on the external trigger pin, TSADTRG. a
• a periodic trigger, which is defined by programming the TRGPER field in the “ADC Trigger
continuous trigger, meaning the ADC Controller restarts the next sequence as soon as it
finishes the current one
Register”.
trigger
start
delay
“ADC Trigger Register”
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