SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 500

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

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DMAC Software Requirements
SAM9X25
SAM9X25
• There must not be any write operation to Channel registers in an active channel after the
• When destination peripheral is defined as the flow controller, source single transfer request
• When Source Peripheral is flow controller, destination single transfer request are not serviced
• When destination peripheral is defined as the flow controller, if the destination width is
• When a Memory to Peripheral transfer occurs if the destination peripheral is flow controller,
• You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte,
• After the software disables a channel by writing into the channel disable register, it must re-
• If you program the BTSIZE field in the DMAC_CTRLA, as zero, and the DMAC is defined as
• When hardware handshaking interface protocol is fully implemented, a peripheral is expected
• Multiple Transfers involving the same peripheral must not be programmed and enabled on
• When a Peripheral is flow controller, the targeted DMAC Channel must be enabled before the
• When AUTO Field is set to TRUE, then the BTSIZE Field is automatically reloaded from its
channel enable is made HIGH. If any channel parameters must be reprogrammed, this can
only be done after disabling the DMAC channel.
are not serviced until Destination Peripheral has asserted its Last Transfer Flag.
until Source Peripheral has asserted its Last Transfer Flag.
smaller than the source width, then a data loss may occur, and the loss is equal to Source
Single Transfer size in bytes- destination Single Transfer size in bytes.
then a prefetch operation is performed. It means that data are extracted from memory before
any request from the peripheral is generated.
half-word and word aligned address depending on the source width and destination width.
enable the channel only after it has polled a 0 in the corresponding channel enable status
register. This is because the current AHB Burst must terminate properly.
the flow controller, then the channel is automatically disabled.
to deassert any sreq or breq signals on receiving the ack signal irrespective of the request
the ack was asserted in response to.
different channel, unless this peripheral integrates several hardware handshaking interface.
Peripheral. If you do not ensure this the DMAC Channel might miss a Last Transfer Flag, if
the First DMAC request is also the last transfer.
previous value. BTSIZE must be initialized to a non zero value if the first transfer is initiated
with AUTO field set to TRUE even if LLI mode is enabled because the LLI fetch operation will
not update this field.
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11