SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 1104

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.13.2
46.14 SMC Timings
46.14.1
1104
1104
SAM9X25
SAM9X25
Power-Up Sequence
Timing Conditions
Figure 46-2.
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that
these power sources reach their target values prior to the release of POR.
The T
(44KHz).
As a conclusion, establish VDDIOP and VDDIOM first, then VDDPLL, and VDDCORE at last, to
ensure a reliable operation of the device.
SMC Timings are given for MAX corners.
• VDDIOP must be
• VDDIOM must reach V
• VDDPLL is to be established prior to VDDCORE to ensure the PLL is powered once enabled
at the latest, after VDDCORE has reached
(Tres +T1 +T2) at the latest, after VDDCORE has reached
into the ROM code.
– T
– T1 = 3 x T
– T2 = 16 x T
– T
– T1 = 66 μs
– T2 = 352 μs
SLCK
RES
RES
VDDCOREtyp
min (22 μs) is obtained for the maximum frequency of the internal RC oscillator
Core Supply POR Output
is a POR characteristic
= 30 μs
VDDIOtyp
VDD (V)
VDDCORE and VDDIO Constraints at Startup
SLCK
Vth+
Voh
Vih
SLCK
SLCK
V
ih
OH
(refer to DC characteristics,
(refer to DC characteristics,
<--- Tres --->
V
th+
.
< T1 >
Table
<------------ T2----------->
Table
46-2, for more details), (Tres + T1)
V
th+
46-2, for more details),
VDDIO > Vih
VDDIO > Voh
VDDCORE
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
VDDIO
t