SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 967

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SAM9X25

Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9X25

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Figure 42-3. EOCx and DRDY Flag Behavior
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
EOCx
DRDY
CHx
Write the ADC_CR
with START = 1
If the ADC_CDR is not read before further incoming data is converted, the corresponding Over-
run Error (OVREx) flag is set in the Overrun Status Register (ADC_OVER).
Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error)
in ADC_SR.
The OVREx flag is automatically cleared when ADC_OVER is read, and GOVRE flag is auto-
matically cleared when ADC_SR is read.
Read the ADC_CDRx
Write the ADC_CR
with START = 1
Read the ADC_LCDR
SAM9X25
SAM9X25
967
967

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