SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 1049

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45.4.13
45.4.13.1
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Physical Interface
RMII Transmit and Receive Operation
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read
clause 45 PHYs, bits[31:28] should be written as 0x0011. For a description of MDC generation,
see the network configuration register in the
Depending on products, the Ethernet MAC is capable of interfacing to RMII or MII Interface. The
RMII bit in the EMAC_USRIO register controls the interface that is selected. When this bit is set,
the RMII interface is selected, else the MII interface is selected.
The MII and RMII interfaces are capable of both 10 Mb/s and 100 Mb/s data rates as described
in the IEEE 802.3u standard. The signals used by the MII interface are described in
Table 45-6.
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It
uses 2 bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a
Transmit Enable (ETXEN), a Receive Error (ERXER), a Carrier Sense (ECRS_DV), and a 50
MHz Reference Clock (ETXCK_EREFCK) for 100Mb/s data rate.
The same signals are used internally for both the RMII and the MII operations. The RMII maps
the signals in a more pin-efficient manner. The transmit and receive bits are converted from a 4-
bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense
and data valid signals are combined into the ECRSDV signal. This signal contains information
on carrier sense, FIFO status, and validity of the data. Transmit error bit (ETXER) and collision
detect (ECOL) are not used in RMII mode.
Pin Name
ETXCK_EREFCK
ECRS
ECOL
ERXDV
ERX0 - ERX3
ERXER
ERXCK
ETXEN
ETX0-ETX3
ETXER
Pin Configuration
ERX0 - ERX3: 4-bit Receive Data
ETX0 - ETX3: 4-bit Transmit Data
ETXEN: Transmit Enable
ETXCK: Transmit Clock
ERXCK: Receive Clock
ECOL: Collision Detect
ETXER: Transmit Error
ERXER: Receive Error
ECRS: Carrier Sense
ERXDV: Data Valid
“Network Control Register” on page
MII
SAM9X25
SAM9X25
1055.
Table
45-6.
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