SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 774

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 38-28. Clock Synchronization in Read Mode
Notes:
Figure 38-29. Clock Synchronization in Write Mode
774
774
TWI_THR
TXCOMP
SVREAD
Clock Synchronization in Write Mode
SCLWS
SVACC
TXRDY
TWI_RHR
TWCK
TXCOMP
SVREAD
SCLWS
RXRDY
SVACC
1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowl-
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
3. SCLWS is automatically set when the clock synchronization mechanism is started.
TWCK
TWD
SAM9X25
SAM9X25
edged or non acknowledged.
SADR.
1
2
S
S
S
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
As soon as a START is detected
SADR
SADR
As soon as a START is detected
The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or
REPEATED_START condition was not detected, it is tied low until TWI_RHR is read.
Figure 38-29 on page 774
DATA0
DATA0
R
W
Write THR
A
A
1
DATA0
DATA0
CLOCK is tied low by the TWI as long as RHR is full
A
A
describes the clock synchronization in Read mode.
DATA1
DATA1
DATA1
DATA0 is not read in the RHR
CLOCK is tied low by the TWI
SCL is stretched on the last bit of DATA1
as long as THR is empty
A
Rd DATA0
XXXXXXX
2
DATA2
A
DATA2
Rd DATA1
DATA1
Ack or Nack from the master
DATA2
NA
NA
Rd DATA2
DATA2
S
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
S
ADR