SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 28

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SAM9X25

Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9X25

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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SAM9X25
SAM9X25
• Write Buffer
• DCache Write-back Buffer
• Memory Management Unit (MMU)
• Memory Access
• Bus Interface Unit
– Write-though and Write-back Operation for DCache Only
– Pseudo-random or Round-robin Replacement
– Cache Lockdown Registers
– Cache Maintenance
– 16-word Data Buffer
– 4-address Address Buffer
– Software Control Drain
– 8 Data Word Entries
– One Address Entry
– Software Control Drain
– Access Permission for Sections
– Access Permission for Large Pages and Small Pages
– 16 Embedded Domains
– 64 Entry Instruction TLB and 64 Entry Data TLB
– 8-, 16-, and 32-bit Data Types
– Separate AMBA AHB Buses for Both the 32-bit Data Interface and the 32-bit
– Arbitrates and Schedules AHB Requests
– Enables Multi-layer AHB to be Implemented
– Increases Overall Bus Bandwidth
– Makes System Architecture Mode Flexible
Instructions Interface
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11

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