SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 225

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 23-6. Input Debouncing Filter Timing
23.5.10
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Divided Slow Clock
if PIO_IFSR = 0
if PIO_IFSR = 1
PIO_PDSR
PIO_PDSR
Pin Level
Input Edge/Level Interrupt
up to 2 cycles Tmck
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a
level on an I/O line. The Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt
Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and dis-
able the input change interrupt by setting and clearing the corresponding bit in PIO_IMR
(Interrupt Mask Register). As Input change detection is possible only by comparing two succes-
sive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input
Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an
input only, controlled by the PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional Interrupt modes can be enabled/disabled by writing in the PIO_AIMER (Addi-
tional Interrupt Modes Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable
Register). The current state of this selection can be read through the PIO_AIMMR (Additional
Interrupt Modes Mask Register)
These Additional Modes are:
In order to select an Additional Interrupt Mode:
• Rising Edge Detection
• Falling Edge Detection
• Low Level Detection
• High Level Detection
• The type of event detection (Edge or Level) must be selected by writing in the set of registers;
• The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected
PIO_ESR (Edge Select Register) and PIO_LSR (Level Select Register) which enable
respectively, the Edge and Level Detection. The current status of this selection is accessible
through the PIO_ELSR (Edge/Level Status Register).
by writing in the set of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and
PIO_REHLSR (Rising Edge/High Level Select Register) which allow to select Falling or
Rising Edge (if Edge is selected in the PIO_ELSR) Edge or High or Low Level Detection (if
up to 2 cycles Tmck
PIO_IFCSR = 1
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 2 cycles Tmck
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
SAM9X25
SAM9X25
up to 2 cycles Tmck
225
225