SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 226

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 23-7. Event Detector on Input Lines (Figure represents line 0)
23.5.10.1
226
226
Resynchronized input on line 0
SAM9X25
SAM9X25
Example
When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Inter-
rupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller
interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired
together to generate a single interrupt signal to the Advanced Interrupt Controller (AIC).
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that
all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is
enabled on a “Level”, the interrupt is generated as long as the interrupt source is not cleared,
even if some read accesses in PIO_ISR are performed.
If generating an interrupt is required on the following:
The configuration required is described below.
• Rising edge on PIO line 0
• Falling edge on PIO line 1
• Rising edge on PIO line 2
• Low Level on PIO line 3
• High Level on PIO line 4
• High Level on PIO line 5
• Falling edge on PIO line 6
• Rising edge on PIO line 7
• Any edge on the other lines
Level is selected in the PIO_ELSR). The current status of this selection is accessible through
the PIO_FRLHSR (Fall/Rise - Low/High Status Register).
PIO_REHLSR[0]
PIO_FELLSR[0]
Rising Edge
Falling Edge
High Level
Detector
Low Level
Detector
Detector
Detector
Detector
Edge
PIO_FRLHSR[0]
0
0
1
1
PIO_LSR[0]
PIO_ESR[0]
PIO_ELSR[0]
1
0
PIO_AIMER[0]
PIO_AIMDR[0]
PIO_AIMMR[0]
1
0
Event detection on line 0
Event Detector
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11