SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 1119

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.16.4.2
Table 46-38. EMAC Signals Relative to EMDC
Notes:
Figure 46-20. Min and Max access time of EMAC output signals
46.16.4.3
Table 46-39. EMAC MII Timings
Notes:
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Symbol
EMAC
EMAC
EMAC
Symbol
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC rising
1. VDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF
2. See Note
edge and the signal change. The Max access timing is the time between the EDMC rising edge and the signal stabilizes.
Figure 46-20
Timing constraints
MII Mode
EMDC
EMDIO
(4)
Parameter
Setup for EMDIO from EMDC rising
Hold for EMDIO from EMDC rising
EMDIO toggling from EMDC rising
Parameter
Setup for ECOL from ETXCK rising
Hold for ECOL from ETXCK rising
Setup for ECRS from ETXCK rising
Hold for ECRS from ETXCK rising
ETXER toggling from ETXCK rising
ETXEN toggling from ETXCK rising
ETX toggling from ETXCK rising
Setup for ERX from ERXCK
Hold for ERX from ERXCK
Setup for ERXER from ERXCK
Hold for ERXER from ERXCK
Setup for ERXDV from ERXCK
Hold for ERXDV from ERXCK
of
illustrates Min and Max accesses for EMAC3.
Table
46-38.
EMAC
4
EMAC
EMAC
1
5
EMAC
2
Min (ns)
Min (ns)
0 ns
EMAC
10 ns
10 ns
10
10
10
10
10
10
10
10
10
10
10
10
10
EMAC
(2)
(2)
(2)
(1)
3 min
3 max
SAM9X25
SAM9X25
Max (ns)
Max (ns)
300 ns
25
25
25
(2)
(2)
(2)
(1)
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