MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 54

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.7 Internal Register Maps
3-18
MOTOROLA
Each address space boundary condition is outlined by the statements that follow. Con-
sider Figure 3-5 and the relationship between CPU address line 19 and IMB address
lines [23:20] when examining these boundary conditions. The first boundary condition
occurs when the CPU16 drives $7FFFF onto its address bus and is derived as follows.
The second boundary condition occurs when the CPU16 drives $80000 onto its ad-
dress bus and is derived as follows.
As the above boundary conditions illustrate, addresses between $080000 and
$F7FFFF will never be seen on the IMB of a CPU16 derivative. At no time will IMB ad-
dress lines [23:19] be driven to states opposite that of CPU address line 19.
It is important to note that this gap is present on the IMB only. The CPU16 simply sees
a flat one megabyte memory map from $00000 to $FFFFF, and user software need
only generate 20-bit effective addresses to access any location in this range.
In Figures 3-6 and 3-7, IMB address lines [23:20] are represented by the letter Y. The
value of Y is equal to %M111, where M is the logic state of the module mapping (MM)
bit in the single-chip integration module configuration register (SCIMCR).
As discussed in 3.6 CPU16 Memory Mapping, CPU16 address lines [19:0] drive IMB
address lines [19:0] and CPU16 address line 19 drives IMB address lines [23:20]. For
this reason, addresses between $080000 and $F7FFFF will never be seen on the IMB.
Setting MM to logic 0 on the MC68HC16R1 and MC68HC916R1 would map the con-
trol registers from $7FF700 to $7FFC3F where they would be inaccessible until a reset
occurs.
As long as MM is set to logic 1, MCU control registers will be accessible, and the
CPU16 need only generate 20-bit effective addresses to access them. Thus to access
SCIMCR, which is mapped at IMB address $YFFA00, the CPU16 must generate the
20-bit effective address $FFA00.
1. If CPU ADDR[19:0] = $7FFFF = %0111 1111 1111 1111 1111
2. Then CPU ADDR19 = %0 and IMB ADDR19 = %0
3. Consequently, IMB ADDR[23:20] = %0000 = $0
4. Thus IMB ADDR[23:0] = $07FFFF = %0000 0111 1111 1111 1111 1111
1. If CPU ADDR[19:0] = $80000 = %1000 0000 0000 0000 0000,
2. Then CPU ADDR19 = %1 and IMB ADDR19 = %1
3. Consequently, IMB ADDR[23:20] = %1111 = $F,
4. Thus IMB ADDR[23:0] = $F80000 = %1111 1000 0000 0000 0000 0000
MM must remain set to logic 1 on all CPU16 derivatives in order for
MCU control registers to remain accessible.
NOTE
MC68HC16Y3/916Y3
USER’S MANUAL