MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 335

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC16Y3/916Y3
USER’S MANUAL
Num
27A
29A
30A
39A
46A
47A
47B
100
101
102
103
28
29
30
31
33
35
37
39
46
48
53
54
55
70
71
72
73
74
75
76
77
78
Late BERR, HALT Asserted to Clock Low (Setup Time)
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
DS, CS Negated to Data In Invalid (Data In Hold)
DS, CS Negated to Data In High Impedance
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLKOUT Low to Data In High Impedance
DSACK[1:0] Asserted to Data In Valid
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted
BGACK Asserted to BG Negated
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
Clock Low to Data Bus Driven (Show Cycle)
Data Setup Time to Clock Low (Show Cycle)
Data Hold from Clock Low (Show Cycle)
BKPT Input Setup Time
BKPT Input Hold Time
Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
RESET Assertion Time
RESET Rise Time
CLKOUT High to Phase 1 Asserted
CLKOUT High to Phase 2 Asserted
Phase 1 Valid to AS or DS Asserted
Phase 2 Valid to AS or DS Asserted
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
(V
DD
and V
13
12
Table A-6 AC Timing (Continued)
Characteristic
DDSYN
ELECTRICAL CHARACTERISTICS
10
= 5.0 Vdc
14
14
14
14
9
7
7, 8
10%, V
11
7
7
SS
= 0 Vdc, T
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
BRAGA
t
t
t
t
t
t
SCLDD
SCLDH
t
t
t
CLBAN
SCLDS
t
CHP1A
CHP2A
P1VSA
P2VSN
BELCL
t
t
t
t
t
GAGN
RWAS
t
t
DOCH
CHDH
t
t
SNDN
CLDH
DABA
RADC
RSTR
BKST
BKHT
RSTA
SNDI
SHDI
DADI
CLDI
t
RWA
AIST
AIHT
MSH
t
MSS
A
GH
GA
= T
L
to T
Min
150
20
15
90
15
40
15
10
15
10
20
10
10
H
—
—
—
—
—
—
—
0
0
1
1
2
1
5
0
0
0
4
3
3
)
1
Max
80
55
90
50
29
30
28
29
10
40
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MOTOROLA
2
Unit
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc
cyc
A-9