MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 384

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

EXOFF — External Clock Off
FRZSW — Freeze Software Enable
CPUD — CPU Development Support Disable
FRZBM — Freeze Bus Monitor Enable
SHEN[1:0] — Show Cycle Enable
SUPV — Supervisor/User Data Space
MM — Module Mapping
D-6
MOTOROLA
CPUD is cleared to zero when the MCU is in an expanded mode, and set to one in
single-chip mode.
The SHEN field determines how the external bus is driven during internal transfer
operations. A show cycle allows internal transfers to be monitored externally.
Table D-3 indicates whether show cycle data is driven externally, and whether exter-
nal bus arbitration can occur. To prevent bus conflict, external devices must not be
selected during show cycles.
This bit has no effect because the CPU16 always operates in the supervisor mode.
The logic state of the MM determines the value of ADDR23 for IMB module addresses.
Because ADDR[23:20] are driven to the same state as ADDR19, MM must be set to
one. If MM is cleared, IMB modules are inaccessible to the CPU16. This bit can be
written only once after reset.
0 = The CLKOUT pin is driven during normal operation.
1 = The CLKOUT pin is placed in a high-impedance state.
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
0 = Instruction pipeline signals available on pins IPIPE1 and IPIPE0.
1 = Pins IPIPE1 and IPIPE0 placed in high-impedance state unless a breakpoint
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
continue to operate, allowing interrupts during background debug mode.
are disabled, preventing interrupts during background debug mode.
occurs.
SHEN[1:0]
00
01
10
11
Table D-3 Show Cycle Enable Bits
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
REGISTER SUMMARY
Action
MC68HC16Y3/916Y3
USER’S MANUAL