MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet
MC68HC916Y3CFT16
Specifications of MC68HC916Y3CFT16
Related parts for MC68HC916Y3CFT16
MC68HC916Y3CFT16 Summary of contents
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MC68HC916Y3 USER’S MANUAL THIS DOCUMENT IS PRODUCED FOR ON-LINE DISTRIBUTION ONLY NOT AVAILABLE AT THE MOTOROLA LITERATURE DISTRIBUTION CENTER. ORDERING INFORMATION IS NOT INCLUDED. PLEASE DIRECT ANY QUESTIONS CONCERNING THIS DOCUMENTATION TO A REPRESENTATIVE AT YOUR LOCAL MOTOROLA ...
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Symbols and Operators ............................................................................. 2-1 2.2 CPU16 Register Mnemonics ..................................................................... 2-2 2.3 Pin and Signal Mnemonics ........................................................................ 2-3 2.4 Register Mnemonics .................................................................................. 2-5 2.5 Conventions .............................................................................................. 2-9 3.1 MC68HC16Y3/916Y3 MCU Features ....................................................... 3-1 3.1.1 Central Processing Unit (CPU16) ...................................................... ...
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Multiply and Accumulate Registers ................................................... 4-5 4.3 Memory Management ............................................................................... 4-5 4.3.1 Address Extension ............................................................................ 4-6 4.3.2 Extension Fields ................................................................................ 4-6 4.4 Data Types ................................................................................................ 4-6 4.5 Memory Organization ................................................................................ 4-7 4.6 Addressing Modes ..................................................................................... 4-8 4.6.1 Immediate Addressing ...
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Background Debug Mode ................................................................ 4-42 4.14.5 Enabling BDM ................................................................................. 4-42 4.14.5.1 BDM Sources .......................................................................... 4-42 4.14.5.2 Entering BDM .......................................................................... 4-43 4.14.5.3 BDM Commands ..................................................................... 4-43 4.14.5.4 Returning from BDM ............................................................... 4-44 4.14.5.5 BDM Serial Interface ............................................................... 4-44 4.15 Recommended ...
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Function Codes ....................................................................... 5-24 5.5.1.8 Data Size Acknowledge Signals ............................................. 5-24 5.5.1.9 Bus Error Signal ...................................................................... 5-25 5.5.1.10 Halt Signal ............................................................................... 5-25 5.5.1.11 Autovector Signal .................................................................... 5-25 5.5.2 Dynamic Bus Sizing ........................................................................ 5-25 5.5.3 Operand Alignment ......................................................................... 5-27 5.5.4 ...
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Power-On Reset .............................................................................. 5-53 5.7.8 Use of the Three-State Control Pin ................................................. 5-54 5.7.9 Reset Processing Summary ............................................................ 5-54 5.7.10 Reset Status Register ..................................................................... 5-55 5.8 Interrupts ................................................................................................. 5-55 5.8.1 Interrupt Exception Processing ....................................................... 5-56 5.8.2 Interrupt Priority and ...
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Low-Power Stop Mode Operation ............................................................. 7-3 7.6 ROM Signature .......................................................................................... 7-3 7.7 Reset ......................................................................................................... 7-3 SECTION 8FLASH EEPROM MODULE 8.1 Flash EEPROM Control Block ................................................................... 8-1 8.2 Flash EEPROM Array ............................................................................... 8-2 8.3 Flash EEPROM Operation ........................................................................ 8-2 8.3.1 ...
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Analog Subsystem .................................................................................. 10-4 10.6.1 Multiplexer ....................................................................................... 10-5 10.6.2 Sample Capacitor and Buffer Amplifier ........................................... 10-5 10.6.3 RC DAC Array ................................................................................. 10-6 10.6.4 Comparator ..................................................................................... 10-6 10.7 Digital Control Subsystem ....................................................................... 10-6 10.7.1 Control/Status Registers ................................................................. 10-6 10.7.2 Clock ...
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Transmit RAM ......................................................................... 11-8 11.3.2.3 Command RAM ....................................................................... 11-9 11.3.3 QSPI Pins ........................................................................................ 11-9 11.3.4 QSPI Operation ............................................................................... 11-9 11.3.5 QSPI Operating Modes ................................................................. 11-10 11.3.5.1 Master Mode ......................................................................... 11-17 11.3.5.2 Master Wrap-Around Mode ................................................... 11-20 11.3.5.3 Slave Mode ...
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SPI Operating Modes ...................................................................... 12-7 12.3.3.1 Master Mode ........................................................................... 12-7 12.3.3.2 Slave Mode ............................................................................. 12-8 12.3.4 SPI Clock Phase and Polarity Controls ........................................... 12-9 12.3.4.1 CPHA = 0 Transfer Format ..................................................... 12-9 12.3.4.2 CPHA = 1 Transfer Format ................................................... ...
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GPT Interrupts ................................................................................. 13-5 13.5 Pin Descriptions ...................................................................................... 13-7 13.5.1 Input Capture Pins ........................................................................... 13-7 13.5.2 Input Capture/Output Compare Pin ................................................. 13-7 13.5.3 Output Compare Pins ...................................................................... 13-7 13.5.4 Pulse Accumulator Input Pin ........................................................... 13-8 13.5.5 Pulse-Width Modulation .................................................................. ...
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Pulse-Width Modulation (PWM) ...................................................... 14-8 14.4.5 Synchronized Pulse-Width Modulation (SPWM) ............................. 14-8 14.4.6 Period Measurement with Additional Transition Detect (PMA) ....... 14-8 14.4.7 Period Measurement with Missing Transition Detect (PMM) .......... 14-8 14.4.8 Position-Synchronized Pulse Generator (PSP) ............................... 14-9 ...
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C.1 M68MMDS1632 Modular Development System ...................................... C-1 C.2 M68MEVB1632 Modular Evaluation Board .............................................. C-1 APPENDIX D REGISTER SUMMARY D.1 Central Processing Unit ............................................................................ D-1 D.1.1 Condition Code Register .................................................................. D-3 D.2 Single-Chip Integration Module 2 ............................................................. D-4 D.2.1 SCIM Configuration ...
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D.3.2 RAM Test Register ......................................................................... D-26 D.3.3 Array Base Address Registers ....................................................... D-26 D.4 Masked ROM Module ............................................................................. D-27 D.4.1 Masked ROM Module Configuration Register ................................ D-27 D.4.2 ROM Array Base Address Registers .............................................. D-29 D.4.3 ROM Signature Registers .............................................................. ...
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D.8.4 MCCI Interrupt Vector Register ...................................................... D-64 D.8.5 SPI Interrupt Level Register ........................................................... D-64 D.8.6 MCCI Pin Assignment Register ...................................................... D-65 D.8.7 MCCI Data Direction Register ........................................................ D-66 D.8.8 MCCI Port Data Registers .............................................................. D-67 D.8.9 SCI Control Register 0 ...
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D.10.11 Channel Interrupt Status Register .................................................. D-94 D.10.12 Link Register .................................................................................. D-94 D.10.13 Service Grant Latch Register ......................................................... D-94 D.10.14 Decoded Channel Number Register .............................................. D-94 D.10.15 TPUMCR2 Module Configuration Register 2 ................................. D-94 D.10.16 TPU2 Parameter RAM ................................................................... D-96 ...
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Figure 3-1 MC68HC16Y3 Block Diagram ........................................................................ 3-4 3-2 MC68HC916Y3 Block Diagram ...................................................................... 3-5 3-3 MC68HC16Y3 Pin Assignment for 160-Pin Package ..................................... 3-6 3-4 MC68HC916Y3 Pin Assignment for 160-Pin Package ................................... 3-7 3-5 Address Bus Connections Between the CPU16 and IMB ...
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Figure 8-1 Programming Flow ......................................................................................... 8-5 8-2 Erasure Flow .................................................................................................. 8-7 9-1 TPUFLASH Programming Flow ..................................................................... 9-6 9-2 TPUFLASH Erasure Flow .............................................................................. 9-8 10-1 ADC Block Diagram ..................................................................................... 10-2 10-2 8-Bit Conversion Timing ............................................................................. 10-12 10-3 10-Bit Conversion Timing ........................................................................... ...
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Figure A-2 External Clock Input Timing Diagram ........................................................... A-11 A-3 ECLK Output Timing Diagram ...................................................................... A-11 A-4 Read Cycle Timing Diagram ........................................................................ A-12 A-5 Write Cycle Timing Diagram ......................................................................... A-13 A-6 Fast Termination Read Cycle Timing Diagram ............................................ A-14 A-7 ...
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Table 1-1 MC68HC16Y3/916Y3 Modules ....................................................................... 1-1 3-1 MC68HC16Y3/MC68HC916Y3 Pin Characteristics ........................................ 3-8 3-2 MC68HC16Y3/MC68HC916Y3 Driver Types................................................ 3-12 3-3 MC68HC16Y3/MC68HC916Y3 Pin Functions .............................................. 3-13 4-2 Instruction Set Summary ............................................................................... 4-12 4-3 Instruction Set Abbreviations and Symbols................................................... 4-30 4-4 CPU16 Implementation of ...
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Table 7-1 ROM Array Space Field .................................................................................. 7-2 7-2 Wait States Field ............................................................................................. 7-3 9-1 Bootstrap Vector Assignments ........................................................................ 9-3 9-2 TPUFLASH Erase Operation Address Ranges............................................... 9-4 10-1 FRZ Field Selection....................................................................................... 10-4 10-2 Multiplexer Channel Sources ........................................................................ 10-5 10-3 Prescaler ...
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Table A-10 SPI Timing..................................................................................................... A-26 A-11 General Purpose Timer AC Characteristics .................................................. A-29 A-12 ADC Maximum Ratings ................................................................................. A-38 A-13 ADC DC Electrical Characteristics (Operating) ............................................. A-39 A-14 ADC AC Characteristics (Operating)............................................................. A-39 A-15 ADC Conversion Characteristics (Operating)................................................ A-40 A-16 ...
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Table D-35 Examples of SCI Baud Rates........................................................................D-49 D-36 PQSPAR Pin Assignments............................................................................D-53 D-37 Effect of DDRQS on QSM Pin Function ........................................................D-54 D-38 Bits Per Transfer ...........................................................................................D-55 D-39 Examples of SCK Frequencies .....................................................................D-56 D-40 MCCI Address Map .......................................................................................D-62 D-41 Interrupt Vector Sources ...
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SECTION 1INTRODUCTION The MC68HC16Y3 and the MC68HC916Y3 microcontrollers are high-speed 16-bit control units that are upwardly code compatible with M68HC11 controllers. Both are members of the M68HC16 Family of modular microcontrollers. M68HC16 microcontroller units (MCUs) are built up from standard ...
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Documentation for the Modular Microcontroller Family follows the modular construc- tion of the devices in the product line. Each device has a comprehensive user’s man- ual that provides sufficient information for normal operation of the device. The user’s manual is ...
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SECTION 2NOMENCLATURE The following tables show the nomenclature used throughout the MC68HC16Y3/ 916Y3 User’s Manual. 2.1 Symbols and Operators Symbol - / • NOT : « MC68HC16Y3/916Y3 USER’S MANUAL Function Addition Subtraction (two’s complement) or negation Multiplication Division ...
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CPU16 Register Mnemonics Mnemonic CCR XMSK YMSK MOTOROLA 2-2 Register ...
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Pin and Signal Mnemonics Mnemonic ADDR[23:0] AN[7:0] AS BERR BG BGACK BKPT BR CLKOUT CS[10:5], CS3 CSBOOT CSE CSM DATA[15:0] DS DSACK[1:0] DSCLK DSI DSO ECLK EXTAL FASTREF FC[2:0] FREEZE HALT IC[3:1] IPIPE[1:0] IRQ[7:1] MISO MOSI OC[5:1] PA[7:0] PADA[7:0] ...
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Mnemonic PGP[7:0] PH[7:0] PQS[5:0] PWMA PWMB QUOT R/W RESET RXDA RXDB SCK SIZ[1:0] SS TSC TXDA TXDB V /V DDA SSA V /MODCLK/V DDSYN SSSYN V FPE STBY XFC XTAL MOTOROLA ...
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Register Mnemonics Mnemonic ADCMCR ADTEST ADCTL[0:1] ADSTAT CFORC CFSR[0:3] CIER CISR CPR[0:1] CREG CR[0:F] CSBARBT CSBAR[0:10] CSORBT CSOR[0:10] CSPAR[0:1] DCNR DDRAB DDRE DDRF DDRG DDRGP DDRH DDRM DDRQS DREG DSCR DSSR FEE[1:3]BAH FEE[1:3]BAL FEE[1:3]BS[0:3] FEE[1:3]CTL FEE[1:3]MCR FEE[1:3]TST GPTMCR GPTMTR ...
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Mnemonic LR LJSRR[0:7] LJURR[0:7] MIVR MMCR MPAR MRMCR MTEST OC1D OC1M PACNT PACTL PEPAR PFIVR PFLVR PFPAR PICR PITR PORTA PORTADA PORTB PORTC PORTE[0:1] PORTF[0:1] PORTG PORTGP PORTH PORTF PORTFE PORTMC PORTMCP PORTQS PQSPAR PRESCL PWMA PWMB PWMBUFA PWMBUFB PWMC ...
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Mnemonic QTEST RAMBAH RAMBAL RAMMCR RAMTST RJURR[0:7] ROMBAH ROMBAL ROMBS[0:3] RR[0:F] RSR SCCR[0:1] SCCR[0:1] SCDR SCSR SCIM2CR SCIM2TR SCIM2TRE SIGHI SIGLO SCCR0[A:B] SCCR1[A:B] SCDR[A:B] SCDR SCSR[A:B] SGLR SPCR SPDR SPSR SPSR SWSR SYNCR SYPCR TCNT TCR TCTL[1:2] TFBAH TFBAL TFBS[0:3] ...
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Mnemonic TI4/O5 TIC[1:3] TICR TMSK[1:2] TOC[1:4] TPUMCR TPUMCR2 TR[0:F] TSTMSRA TSTMSRB TSTRC TSTSC MOTOROLA 2-8 Register GPT Timer Input Capture 4/Output Compare 5 Register GPT Timer Input Capture Registers [1:3] TPU2 Interrupt Configuration Register GPT Timer Mask Register [1:2] GPT ...
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Conventions Logic level one is the voltage that corresponds to a Boolean true (1) state. Logic level zero is the voltage that corresponds to a Boolean false (0) state. Set refers specifically to establishing logic level one on a ...
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MOTOROLA 2-10 MC68HC16Y3/916Y3 USER’S MANUAL ...
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This section provides general information on MC68HC16Y3 and MC68HC916Y3 MCUs. It lists features of each of the modules, shows device functional divisions and pinouts, summarizes signal and pin functions, discusses the intermodule bus, and pro- vides system memory maps. Timing ...
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Masked ROM Module (MRM) — MC68HC16Y3 Only • 96-Kbyte array, accessible as bytes or words • User selectable default base address • User selectable bootstrap ROM function • User selectable ROM verification code 3.1.5 Flash EEPROM Module (FLASH) — ...
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Intermodule Bus The intermodule bus (IMB standardized bus developed to facilitate the design of modular microcontrollers. It contains circuitry that supports exception processing, ad- dress space partitioning, multiple interrupt levels, and vectored interrupts. The stan- dardized modules ...
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TXDA/PMC7 RXDA/PMC6 TXDB/PMC5 RXDB/PMC4 PQS5/PCS2 PQS4/PCS1 PQS3/PCS0/SS PQS2/SCK PQS1/MOSI PQS0/MISO PWMA PWMA PWMB PWMB PCLK PCLK PAI PAI PGP7/IC4/OC5/OC1 IC4/OC5/OC1 PGP6/OC4/OC1 OC4/OC1 PGP5/OC3/OC1 OC3/OC1 PGP4/OC2/OC1 OC2/OC1 PGP3/OC1 OC1 PGP2/IC3 IC3 GPT PGP1/IC2 IC2 PGP0/IC1 IC1 ADC SRAM AN7/PADA7 AN7 AN6/PADA6 ...
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TXDA/PMC7 RXDA/PMC6 TXDB/PMC5 RXDB/PMC4 PQS5/PCS2 PQS4/PCS1 PQS3/PCS0/SS PQS2/SCK PQS1/MOSI PQS0/MISO PWMA PWMA PWMB PWMB PCLK PCLK PAI PAI PGP7/IC4/OC5/OC1 IC4/OC5/OC1 PGP6/OC4/OC1 OC4/OC1 PGP5/OC3/OC1 OC3/OC1 PGP4/OC2/OC1 OC2/OC1 PGP3/OC1 OC1 PGP2/IC3 IC3 GPT PGP1/IC2 IC2 PGP0/IC1 IC1 ADC 4K SRAM AN7/PADA7 AN7 ...
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VSS 121 CSBOOT 122 BR/CS0 123 BG/CSM 124 BGACK/CSE 125 FC0/CS3 126 FC1/CS4 127 FC2/CS5 128 VSS 129 VDD 130 ADDR19/CS6 131 ADDR20/CS7 132 ADDR21/CS8 133 ADDR22/CS9 134 ADDR23/CS10 135 VDD 136 VSS 137 NC 138 BKPT/DSCLK 139 IPIPE1/DSI 140 ...
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VSS 121 CSBOOT 122 BR/CS0 123 BG/CSM 124 BGACK/CSE 125 FC0/CS3 126 FC1 127 FC2/CS5 128 VSS 129 VDD 130 ADDR19/CS6 131 ADDR20/CS7 132 ADDR21/CS8 133 ADDR22/CS9 134 ADDR23/CS10 135 VDD 136 VSS 137 VFPE2 138 BKPT/DSCLK 139 IPIPE1/DSI 140 ...
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Pin Descriptions Table 3-1 summarizes pin characteristics of the MC68HC16Y3 and MC68HC916Y3 MCUs. Entries in the “Associated Module” column indicate to which module individual pins belong. For MCU pins that can be outputs, the “Driver Type” column lists which ...
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Table 3-1 MC68HC16Y3/MC68HC916Y3 Pin Characteristics Pin Mnemonic(s) Number(s) BKPT/DSCLK BR/CS0 CLKOUT CSBOOT DATA0/PH0 DATA1/PH1 DATA2/PH2 DATA3/PH3 DATA4/PH4 DATA5/PH5 DATA6/PH6 DATA7/PH7 DATA8/PG0 DATA9/PG1 DATA10/PG2 DATA11/PG3 DATA12/PG4 DATA13/PG5 DATA14/PG6 DATA15/PG7 DS/PE4 DSACK0/PE0 DSACK1/PE1 4 EXTAL FASTREF/PF0 FC0/CS3/PC0 5 FC1/CS4/PC1 FC2/CS5/PC2 FREEZE/QUOT IC4/OC5/OC1/PGP7 ...
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Table 3-1 MC68HC16Y3/MC68HC916Y3 Pin Characteristics Pin Mnemonic(s) Number(s) OC4/OC1/PGP6 OC3/OC1/PGP5 OC2/OC1/PGP4 OC1/PGP3 6 PAI 6 PCLK PCS2/PQS2 PCS1/PQS1 7 PWMA 7 PWMB R/W RESET RXDA/PMC6 RXDB/PMC4 SS/PCS0/PQS3 SCK/PQS2 SIZ0/PE6 SIZ1/PE7 T2CLK TPUCH0 TPUCH1 TPUCH2 TPUCH3 TPUCH4 TPUCH5 TPUCH6 TPUCH7 TPUCH8 ...
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Table 3-1 MC68HC16Y3/MC68HC916Y3 Pin Characteristics Pin Mnemonic(s) Number( DDA V /MODCLK DDSYN V FPE1 V FPE2 SSA V SSSYN V STBY 4 XFC 4 XTAL NOTES: 1. AN[7:0]/PADA[7:0], FASTREF/PF0, MISO/PQS0, ...
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DATA[15:8]/PG[7:0] and DATA[7:0]/PH[7:0] are only synchronized during reset and when being used as discrete general purpose inputs. 4. EXTAL, XFC, and XTAL are clock connections. 5. CS4 is used only on the MC68HC16Y3. 6. PAI and PCLK can be ...
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Table 3-3 MC68HC16Y3/MC68HC916Y3 Pin Functions Pin Pin Mnemonic(s) Number(s) ADDR0 100 ADDR1 12 ADDR2 13 ADDR3/PB0 14 ADDR4/PB1 15 ADDR5/PB2 16 ADDR6/PB3 17 ADDR7/PB4 18 ADDR8/PB5 19 ADDR9/PB6 20 ADDR10/PB7 21 ADDR11/PA0 23 ADDR12/PA1 24 ADDR13/PA2 25 28 ADDR14/PA3 ADDR15/PA4 ...
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Table 3-3 MC68HC16Y3/MC68HC916Y3 Pin Functions Pin Pin Mnemonic(s) Number(s) DATA0/PH0 119 DATA1/PH1 118 DATA2/PH2 117 DATA3/PH3 116 DATA4/PH4 115 DATA5/PH5 114 DATA6/PH6 113 DATA7/PH7 112 DATA8/PG0 111 DATA9/PG1 110 DATA10/PG2 109 DATA11/PG3 106 105 DATA12/PG4 DATA13/PG5 104 DATA14/PG6 103 DATA15/PG7 ...
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Table 3-3 MC68HC16Y3/MC68HC916Y3 Pin Functions Pin Pin Mnemonic(s) Number(s) IRQ1/PF1 87 IRQ2/PF2 86 IRQ3/PF3 85 IRQ4/PF4 84 IRQ5/PF5 83 IRQ6/PF6 82 IRQ7/PF7 81 MISO/PMC0 35 MOSI/PMC1 34 OC4/OC1/PGP6 149 OC3/OC1/PGP5 150 OC2/OC1/PGP4 151 OC1/PGP3 152 PAI 147 PCLK 144 PCS2/PQS2 ...
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Table 3-3 MC68HC16Y3/MC68HC916Y3 Pin Functions Pin Pin Mnemonic(s) Number(s) TXDA/PMC7 52 TXDB/PMC5 108 120 130 136 143 157 V 9 DDA V /MODCLK 67 DDSYN V 64 FPE1 V ...
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CPU16 Memory Mapping Each member of the M68HC16 family is comprised of a set of modules connected by the intermodule bus (IMB). The full IMB has a 16-bit data bus, a 24-bit address bus, and three function code lines, ...
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Each address space boundary condition is outlined by the statements that follow. Con- sider Figure 3-5 and the relationship between CPU address line 19 and IMB address lines [23:20] when examining these boundary conditions. The first boundary condition occurs when ...
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BYTES $YFF5FF $YFF700 64 BYTES $YFF73F $YFF820 64 KBYTE ROM CONTROL 32 BYTES $YFF83F $YFF840 32 KBYTE ROM CONTROL 32 BYTES $YFF85F $YFF900 64 BYTES $YFF93F $YFFA00 128 BYTES $YFFA7F UNUSED $YFFB00 SRAM CONTROL 8 BYTES $YFFB07 ...
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BYTES $YFF5FF $YFF700 64 BYTES $YFF73F $YFF800 16 KBYTE FLASH EEPROM CONTROL 32 KBYTES $YFF81F $YFF820 48 KBYTE FLASH EEPROM CONTROL 32 KBYTES $YFF83F $YFF840 32 KBYTE FLASH EEPROM CONTROL 32 KBYTES $YFF85F $YFF860 TPU FLASH EEPROM ...
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Address Space Maps Figures 3-8 and 3-9 show CPU16 address space for the MC68HC16Y3 MCU. Figures 3-10 and 3-11 show CPU16 address space for the MC68HC916Y3 MCU. Address space can be split into physically distinct program and data spaces ...
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BANK 0 RESET AND EXCEPTION VECTORS $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM $070000 AND DATA BANK 7 SPACE $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 ...
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BANK 0 $000008 $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM SPACE $070000 BANK 7 $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 BANK 8 $F90000 BANK 9 ...
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BANK 0 RESET AND EXCEPTION VECTORS $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM $070000 AND DATA BANK 7 SPACE $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 ...
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BANK 0 $000008 $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM SPACE $070000 BANK 7 $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 BANK 8 $F90000 BANK 9 ...
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MOTOROLA 3-26 MC68HC16Y3/916Y3 USER’S MANUAL ...
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SECTION 4 CENTRAL PROCESSOR UNIT This section is an overview of the central processor unit (CPU16). For detailed infor- mation, refer to the CPU16 Reference Manual (CPU16RM/AD). 4.1 General The CPU16 provides compatibility with the M68HC11 CPU and also provides ...
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Figure 4-1 CPU16 Register Model MOTOROLA 4 CCR XMSK ...
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Accumulators The CPU16 has two 8-bit accumulators (A and B) and one 16-bit accumulator (E). In addition, accumulators A and B can be concatenated into a second 16-bit double ac- cumulator (D). Accumulators A, B, and D are general-purpose ...
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Condition Code Register The 16-bit condition code register is composed of two functional blocks. The eight MSB, which correspond to the CCR on the M68HC11, contain the low-power stop con- trol bit and processor status flags. The eight LSB ...
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SM — Saturate Mode Bit When SM is set and either set, data read from AM using TMER or TMET is given maximum positive or negative value, depending on the state of the AM sign bit ...
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Address Extension All CPU16 resources used to generate addresses are effectively 20 bits wide. These resources include the index registers, program counter, and stack pointer. All address- ing modes use 20-bit addresses. Twenty-bit addresses are formed from a 16-bit ...
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Signed 36-bit fixed-point numbers are used only by the MAC unit. Bit 35 is the sign bit. Bits [34:31] are sign extension bits. There is an implied radix point between bits 31 and 30. There are 31 bits of magnitude, ...
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Address BIT BIT BIT $0000 $0002 $0004 X OFFSET $0006 BCD1 $0008 $000A $000C $000E $0010 $0012 $0014 (Radix Point) $0016 (Radix Point) $0018 (Radix Point) $001A $001C (Radix Point) $001E « « « ...
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Mode Accumulator Offset Extended Immediate Indexed 8-Bit Indexed 16-Bit Indexed 20-Bit Inherent Post-Modified Index Relative All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an operand or an extension field to form a 20-bit effective address. Access across ...
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The PSHM and PULM instructions use an 8-bit immediate mask operand to indicate which registers must be pushed to or pulled from the stack. 4.6.2 Extended Addressing Modes Regular extended mode instructions contain ADDR[15:0] in the word following the ...
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Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode In M68HC11 systems, the direct addressing mode can be used to perform rapid accesses to RAM or I/O mapped from $0000 to $00FF. The CPU16 uses the first 512 ...
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Table 4-2 Instruction Set Summary Mnemonic Operation Description ABA Add ABX Add (XK : IX) (000 : B) ABY Add (YK : IY) + (000 : B) ABZ Add ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description ADDB Add to B (B) ADDD Add ADDE Add ADE Add (E) + (D) ADX Add D to ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description ANDB AND B (B) (M) ANDD AND D ( ANDE AND E ( AND CCR (CCR) IMM16 1 ANDP ASL Arithmetic Shift Left ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description ASRA Arithmetic Shift Right A ASRB Arithmetic Shift Right B ASRD Arithmetic Shift Right D ASRE Arithmetic Shift Right E ASRM Arithmetic Shift Right AM ASRW Arithmetic Shift Right Word Branch ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description BITB Bit Test B (B) (M) BLE Branch if Less Than Equal to Zero BLS Branch if Lower Same BLT Branch if Less Than ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description BVC Branch if Overflow branch Clear BVS Branch if Overflow Set branch CBA Compare (A) CLR Clear a Byte in ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description CPD Compare D to Memory (D) CPE Compare E to Memory (E) CPS Compare Stack (SP) Pointer to Memory CPX Compare IX to (IX) Memory CPY Compare IY to (IY) Memory ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description EDIVS Extended Signed ( (IX) Integer Divide Quotient Remainder EMUL Extended Unsigned (E) (D) Multiply EMULS Extended Signed (E) (D) Multiply EORA Exclusive OR A (A) EORB Exclusive OR ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description JMP Jump ea JSR Jump to Subroutine Push (PC) (SK SP) $0002 Push (CCR) (SK SP) $0002 ea LBCC Long Branch if Carry branch Clear LBCS Long ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description LDAB Load B (M) LDD Load LDE Load LDED Load Concatenated ( and LDHI Initialize H and I ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description LPSTOP Low Power Stop then STOP else NOP LSR Logical Shift Right LSRA Logical Shift Right A LSRB Logical Shift Right B LSRD Logical Shift Right D LSRE Logical Shift Right ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description ORAA OR A (A) ORAB OR B (B) ORD ORE ORP OR Condition Code (CCR) Register PSHA ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description PULM Pull Multiple Registers For mask bits Mask bits: If mask bit set 0 = CCR[15:4] ( Pull register 2 = ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description RORW Rotate Right Word Return from Interrupt (SK SP RTI Pull CCR (SK SP (PK PC) Return from Subrou- ( RTS ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description STAB Store B STD Store D (D) STE Store E (E) STED Store Concatenated (E) D and E (D) STS Store Stack Pointer (SP) STX Store IX (IX) STY Store IY ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description SUBB Subtract from B (B) SUBD Subtract from D ( SUBE Subtract from E ( SWI Software Interrupt (PK PC) + $0002 Push (PC) ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description TMET Transfer Truncated If (SM ( then Saturation Value else AM[31:16] TMXED Transfer AM to AM[35:32 AM35 AM[31:16] AM[15:0] TPA Transfer CCR to ...
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Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description XGDY Exchange D with IY (D) XGDZ Exchange D with IZ (D) XGEX Exchange E with IX (E) XGEY Exchange E with IY (E) XGEZ Exchange E with IZ (E) NOTES: ...
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Table 4-3 Instruction Set Abbreviations and Symbols A — Accumulator A AM — Accumulator M B — Accumulator B CCR — Condition code register D — Accumulator D E — Accumulator E EK — Extended addressing extension field IR — ...
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Comparison of CPU16 and M68HC11 CPU Instruction Sets Most M68HC11 CPU instructions are a source-code compatible subset of the CPU16 instruction set. However, certain M68HC11 CPU instructions have been replaced by functionally equivalent CPU16 instructions, and some CPU16 instructions ...
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Table 4-4 CPU16 Implementation of M68HC11 CPU Instructions M68HC11 Instruction BHS BCC only BLO BCS only BSR Generates a different stack frame CLC Replaced by ANDP CLI Replaced by ANDP CLV Replaced by ANDP DES Replaced by AIS DEX Replaced ...
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Instruction Format CPU16 instructions consist of an 8-bit opcode that can be preceded by an 8-bit prebyte and followed by one or more operands. Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone. Page 1, 2, ...
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Opcode with 8-Bit Operand Opcode 8-Bit Opcode with 4-Bit Index Extensions Opcode 8-Bit Opcode, Argument( Opcode 8-Bit Opcode with 8-Bit Prebyte, No Argument 15 ...
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IPIPE0 IPIPE1 DATA BUS Figure 4-5 Instruction Execution Model 4.10.1 Microsequencer The microsequencer controls the order in which instructions are fetched, advanced through the pipeline, and executed. It increments the program counter and generates multiplexed external tracking signals IPIPE0 and ...
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Execution Process Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are evaluated in stage B. The execution unit can access operands in either stage A or stage B (stage B accesses are limited to ...
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Total execution time is calculated using the expression: Where: ( Total clock periods per instruction T ( Clock periods used for internal operation I ( Clock periods used for program access P (CL ) ...
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Table 4-5 Exception Vector Table Vector Vector Number Address 0 0000 0002 0004 0006 4 0008 5 000A 6 000C 7 000E 8 0010 9 – E 0012 – 001C F 001E 10 0020 11 0022 12 0024 13 0026 ...
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Exception Processing Sequence Exception processing is performed in four phases. Priority of all pending exceptions is evaluated and the highest priority exception is processed first. Processor state is stacked, then the CCR PK extension field is cleared. An exception ...
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Multiple Exceptions Each exception has a hardware priority based upon its relative importance to system operation. Asynchronous exceptions have higher priorities than synchronous exceptions. Exception processing for multiple exceptions is completed by priority, from highest to lowest. Priority governs ...
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IPIPE0/IPIPE1 Multiplexing Six types of information are required to track pipeline activity. To generate the six state signals, eight pipeline states are encoded and multiplexed into IPIPE0 and IPIPE1. The multiplexed signals have two phases. State signals are active ...
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If BKPT assertion is synchronized with an operand fetch, breakpoint processing occurs at the end of the instruction during which BKPT is latched. Breakpoints on instructions that are flushed from the pipeline before execution are not acknowledged. Operand breakpoints ...
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Entering BDM When the CPU16 detects a breakpoint or decodes a BGND instruction when BDM is enabled, it suspends instruction execution and asserts the FREEZE signal. Once FREEZE has been asserted, the CPU16 enables the BDM serial communication hard- ...
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Returning from BDM BDM is terminated when a resume execution (GO) command is received. GO refills the instruction pipeline from address ( $0006). FREEZE is negated before the first prefetch. Upon negation of FREEZE, the BDM ...
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INSTRUCTION REGISTER BUS RCV DATA LATCH PARALLEL OUT PARALLEL IN SERIAL OUT STATUS EXECUTION UNIT SYNCHRONIZE MICROSEQUENCER Figure 4-7 BDM Serial I/O Block Diagram 4.15 Recommended BDM Connection In order to use BDM development tools when an MCU is installed ...
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Digital Signal Processing The CPU16 performs low-frequency digital signal processing (DSP) algorithms in real time. The most common DSP operation in embedded control applications is filtering, but the CPU16 can perform several other useful DSP functions. These include auto- ...
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SECTION 5 SINGLE-CHIP INTEGRATION MODULE 2 This section is an overview of the single-chip integration module 2 (SCIM2). Refer to the SCIM Reference Manual (SCIMRM/AD) for a comprehensive discussion of SCIM2 capabilities. Refer to D.2 Single-Chip Integration Module 2 for ...
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Single-chip mode, in which the SCIM2 provides seven general purpose I/O ports, no external address or data buses, one general purpose chip-select line, and a boot ROM chip-select line. Although the full IMB supports 24 address and 16 data ...
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Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping (MM) bit in SCIMCR determines where the control register block is located in the system memory ...
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Show Internal Cycles A show cycle allows internal bus transfers to be monitored externally. The SHEN field in SCIMCR determines what the external bus interface does during internal transfer operations. Table 5-1 shows whether data is driven externally, and ...
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The fast reference is typically a 4.194 MHz crystal; the slow reference is typically 32.768 kHz crystal. Each reference frequency may be generated by sources other than a crystal. Keep these sources in mind while reading the rest of this ...
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RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-KHZ CRYSTAL. SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT. Figure 5-3 Slow Reference Crystal Circuit A 4.194 MHz crystal ...
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A voltage controlled oscillator (VCO) in the PLL generates the system clock signal. To maintain a 50% clock duty cycle, the VCO frequency (f the system clock frequency, depending on the state of the X bit in SYNCR. The clock ...
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The synthesizer locks when the VCO frequency is equal the filter time constant and by the amount of difference between the two comparator inputs. Whenever a comparator input changes, the synthesizer must relock. Lock sta- tus is ...
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For the device to perform correctly, both the clock frequency and VCO frequency (selected by the W, X, and Y bits) must be within the limits specified for the MCU. In order for the VCO frequency to be within specifications ...
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Table 5-2 16.78 MHz Clock Control Multipliers (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus [W: Value) VCO Y Slow Fast 000000 4 .03125 000001 8 .0625 000010 12 .09375 000011 16 .125 ...
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Table 5-2 16.78 MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus [W: Value) VCO Y Slow Fast 100000 132 1.03125 100001 136 1.0625 100010 140 1.09375 100011 144 ...
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Table 5-3 16.78 MHz System Clock Frequencies (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus [W: Value) VCO 000000 131 kHz 000001 000010 000011 000100 000101 000110 000111 1049 001000 1180 001001 ...
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Table 5-3 16.78 MHz System Clock Frequencies (Continued) (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus [W: Value) VCO 100000 4325 kHz 100001 4456 100010 4588 100011 4719 100100 4850 100101 4981 ...
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External Bus Clock The state of the E-clock division bit (EDIV) in SYNCR determines clock rate for the E-clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripherals. ECLK frequency can be ...
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The internal oscillator which supplies the input frequency for the PLL always runs when a crystal is used. SETUP INTERRUPT TO WAKE UP MCU FROM LPSTOP NO USING EXTERNAL CLOCK? YES USE SYSTEM CLOCK AS SCIMCLK IN LPSTOP? YES SET ...
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System Protection The system protection block preserves reset status, monitors internal activity, and provides periodic interrupt generation. Figure 5 block diagram of the submodule. 9 CLOCK 2 PRESCALER 5.4.1 Reset Status The reset status register (RSR) latches ...
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BMT[1: The monitor does not check DSACK response on the external bus unless the CPU16 initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. If ...
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Both writes must occur before timeout in the order listed. Any number of instructions can be executed between the two writes. Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the software watchdog timing (SWT[1:0]) field ...
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Table 5-6 Software Watchdog Divide Ratio SWP Figure 5 block diagram of the watchdog timer and the clock control for the periodic interrupt timer. EXTAL XTAL FREEZE CRYSTAL 1 128 ...
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The periodic interrupt timer modulus counter is clocked by one of two signals. When the PLL is enabled (MODCLK = 1 during reset), f oscillator; f 128 is used with fast reference oscillator. When the PLL is disabled ref (MODCLK ...
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The PIRQL field is compared to the CPU16 interrupt priority mask to determine whether the interrupt is recognized. Table 5-8 shows PIRQL[2:0] priority values. Be- cause of SCIM2 hardware prioritization, a PIT interrupt is serviced before an external interrupt request ...
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DSACK1 DSACK0 R/W CS3 CS4 IRQ7 ADDR[17:0] DATA[15: CSBOOT CS0 1 CS1 CS2 NOTES: 1. ALL CHIP-SELECT LINES IN THIS EXAMPLE ...
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The external bus has 24 address lines and 16 data lines. ADDR[19:0] are normal ad- dress outputs; ADDR[23:20] follow the output state of ADDR19. The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and ...
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Read/Write Signal The read/write signal (R/W) determines the direction of the transfer during a bus cycle. This signal changes state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only transitions ...
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Bus Error Signal The bus error signal (BERR) is asserted when a bus cycle is not properly terminated by DSACK or AVEC assertion. It can also be asserted in conjunction with DSACK to indicate a bus error condition, provided ...
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During a a bus transfer cycle, an external device signals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK inputs, as shown in Table 5-11. Chip-select logic can generate data ...
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Operand Alignment The EBI data multiplexer establishes the necessary connections for different combi- nations of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. Positioning of bytes ...
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Table 5-12 Operand Alignment Current Transfer Case Cycle 1 Byte to 8-bit port (even) 2 Byte to 8-bit port (odd) 3 Byte to 16-bit port (even) 4 Byte to 16-bit port (odd) Word to 8-bit port 5 (aligned) Word to ...
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Synchronization to CLKOUT External devices connected to the MCU bus can operate at a clock frequency different from the frequencies of the MCU as long as the external devices satisfy the interface signal timing constraints. Although bus cycles are ...
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Read Cycle During a read cycle, the MCU transfers data from an external memory or peripheral device. If the instruction specifies a long-word or word operation, the MCU attempts to read two bytes at once. For a byte operation, ...
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MCU ADDRESS DEVICE (S0) 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS (S1) PLACE DATA ON DATA[15:0] (S2) ASSERT DS AND WAIT FOR DSACK ...
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Fast termination cycles use internal handshaking signals generated by the chip-select logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. When AS, DS, and R/W are valid, a peripheral device either places data on the ...
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FUNCTION CODE 2 0 BREAKPOINT ACKNOWLEDGE 2 0 LOW POWER STOP BROADCAST 2 0 INTERRUPT ACKNOWLEDGE Figure 5-13 CPU Space Address Encoding 5.6.4.1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at ...
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BREAKPOINT OPERATION FLOW CPU16 ACKNOWLEDGE BREAKPOINT 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] 4) PLACE ALL ONES ON ADDR[4:2] 5) SET ADDR1 TO ONE 6) SET SIZE ...
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BERR during the LPSTOP broadcast cycle is ignored Figure 5-15 LPSTOP Interrupt Mask Level 5.6.5 Bus Exception Control Cycles An external device or a chip-select circuit must assert at least one of ...
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Table 5-13 DSACK, BERR, and HALT Assertion Results Type of Control Termination Signal DSACK NORMAL BERR HALT DSACK HALT BERR HALT DSACK BUS ERROR 1 BERR HALT DSACK BUS ERROR 2 BERR HALT DSACK BUS ERROR 3 BERR HALT DSACK ...
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The external bus interface does not latch data when an external bus cycle is terminated by a bus error. When this occurs during an in- struction prefetch, the IMB precharge state (bus pulled high, or $FF) is latched into the ...
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When the MCU completes a bus cycle while the HALT signal is asserted, the data bus goes into a high-impedance state and the AS and DS signals are driven to their inac- tive states. Address, function code, size, and read/write ...
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This additional BG assertion allows external arbitration circuitry to select the next bus master before the current master has released the bus. Refer to Figure 5-16, which shows bus arbitration for a single device. The flow chart shows BR negated ...
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SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion of the data bus is valid during the cycle. During a byte write to an internal address, the portion of the bus that represents the byte that is ...
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EXTRST (external reset) drives the external reset pin. • CLKRST (clock reset) resets the clock module. • MSTRST (master reset) goes to all other internal circuits. All resets are gated by CLKOUT. Asynchronous resets are assumed to be catastroph- ...
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Table 5-15 Basic Configuration Options Select Pin MODCLK BKPT BERR DATA1 (if BERR = 1) BERR, BKPT, and MODCLK do not have internal pull-ups and must be driven to the desired state during reset. When BERR is high during reset, ...
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Data Bus Mode Selection All data lines have weak internal pull-up devices. When pins are held high by the internal pull-ups, the MCU uses a default operating configuration. However, specific lines can be held low externally during reset to ...
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DATA15 DATA8 DATA7 DATA0 RESET DS R/W Figure 5-17 Preferred Circuit for Data Bus Mode Select Conditioning Alternate methods can be used for driving data bus pins low during reset. Figure 5-18 shows two of these ...
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DATA PIN 1 k 1N4148 RESET Figure 5-18 Alternate Circuit for Data Bus Mode Select Conditioning Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC- TERISTICS. Do not confuse pin function with pin electrical state. Refer to ...
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DATA0 determines the port size of the boot ROM chip-select signal CSBOOT. Unlike other chip-select signals, CSBOOT is active at the release of reset. When DATA0 is held low, port size is 8 bits; when DATA0 is held high, either ...
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Expanded Mode The SCIM2 uses an 8-bit data bus when BERR = 1 and DATA1 = 1 during reset. In this configuration, pins DATA[7:0] are configured as port H, an 8-bit I/O port. Pins DATA[15:8] are configured as ...
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Single-Chip Mode Single-chip operation is selected when BERR = 0 during reset. BERR can be tied low permanently to select this configuration. In single-chip configuration, pins DATA[15:0] are configured as two 8-bit I/O ports, ports G and H. ADDR[18:3] ...
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The MODCLK pin can also be used as parallel I/O pin PF0. To pre- vent inadvertent clock mode selection by logic connected to port F, use an active device to drive MODCLK during reset. 5.7.3.7 Breakpoint Mode Selection Background debug ...
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External ROM emulation is enabled by holding DATA1, DATA10, and DATA13 low during reset (BERR must be held high during reset to enable the ROM module). While ROM emulation mode is enabled, memory chip select signal CSM is asserted when- ...
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Table 5-20 Module Pin Functions 1 Module MCCI NOTES: 1. Module port pins may indeterminate state for milliseconds at power-up. 5.7.5 Pin State During Reset It is important to keep the distinction between pin ...
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Table 5-21 SCIM2 Pin Reset States Pin(s) While RESET CS10/ADDR23/ECLK CS[9:6]/ADDR[22:19]/PC[6:3] ADDR[18:0] AS/PE5 BERR CSM/BG CSE/BGACK CS0/BR CLKOUT CSBOOT DATA[15:0] DS/PE4 DSACK0/PE0 DSACK1/PE1 CS[5:3]/FC[2:0]/PC[2:0] HALT IRQ[7:1]/PF[7:1] FASTREF/PF0 R/W RESET SIZ[1:0]/PE[7:6] TSC 5.7.5.2 Reset States of Pins Assigned to Other MCU ...
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If an internal source asserts a reset signal, the reset control logic asserts the RESET pin for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to ...
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CLKOUT VCO LOCK CLOCKS RESET BUS CYCLES ADDRESS AND BUS STATE CONTROL SIGNALS UNKNOWN THREE-STATED NOTES: 1. INTERNAL START-UP TIME 2. FIRST INSTRUCTION FETCHED 5.7.8 Use of the Three-State Control Pin Asserting the three-state control (TSC) input ...
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Instruction execution is aborted. 2. The condition code register is initialized. a. The IP field is set to $7, disabling all interrupts below priority 7. b. The S bit is set, disabling LPSTOP mode. c. The SM bit is ...
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Interrupt Exception Processing The CPU16 handles interrupts as a type of asynchronous exception. An exception is an event that preempts normal processing. Exception processing makes the transition from normal instruction execution to execution of a routine that deals with ...
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Interrupt requests are sampled on consecutive falling edges of the system clock. In- terrupt request input circuitry has hysteresis valid, a request signal must be as- serted for at least two consecutive clock periods. Valid requests do not ...
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Because the EBI manages external interrupt requests, the SCIM2 IARB value is used for arbitration between internal and external interrupt requests. The reset value of IARB for the SCIM2 is %1111, and the reset IARB value for all other modules ...
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The CPU16 finishes higher priority exception processing or reaches an instruction boundary. 2. Processor state is stacked, then the CCR PK extension field is cleared. 3. The interrupt acknowledge cycle begins: a. FC[2:0] are driven to %111 (CPU space) ...
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Chip-Selects Typical microcontrollers require additional hardware to provide external chip-select signals. The MCU includes 12 programmable chip-select circuits that can provide from clock-cycle access to external memory and peripherals. Address block sizes of 2 Kbytes to ...
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DSACK1 DSACK0 R/W CS3 CS4 IRQ7 ADDR[17:0] DATA[15: CSBOOT CS0 1 CS1 CS2 NOTES: 1. ALL CHIP-SELECT LINES IN THIS EXAMPLE ...
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Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. Logic can also generate DSACK and AVEC signals internally. A single DSACK generator is shared by all chip- selects. Each signal ...
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Chip-Select Registers Each chip-select pin can have one or more functions. Chip-select pin assignment reg- isters CSPAR[1:0] determine functions of the pins. Pin assignment registers also de- termine port size (8- or 16-bit) for dynamic bus allocation. A pin ...
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Table 5-23 Pin Assignment Field Encoding CSxPA[1:0] Port size determines the way in which bus transfers to an external address are allo- cated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as ...
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Table 5-24 Block Size Encoding BLKSZ[2:0] 000 001 010 011 100 101 110 111 NOTES: 1. ADDR[23:20] are the same logic level as ADDR19 during normal operation. The chip-select address compare logic uses only the most significant bits to match ...
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BYTE[1:0] controls bus allocation for chip-select transfers. Port size, set when a chip- select is enabled by a pin assignment register, affects signal assertion. When an 8-bit port is assigned, any BYTE field value other than %00 enables the chip-select ...
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Chip-Select Operation When the MCU makes an access, enabled chip-select circuits compare the following items: • Function codes to SPACE fields, and to the IP mask if the SPACE field encoding is not for CPU space. • Appropriate address ...
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FUNCTION CODE 2 0 INTERRUPT ACKNOWLEDGE Figure 5-22 CPU Space Encoding for Interrupt Acknowledge Because address match logic functions only after the EBI transfers an interrupt acknowledge cycle to the external address bus following IARB contention, chip-select ...
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Chip-Select Reset Operation The least significant bit of each of the 2-bit chip-select pin assignment fields in CSPAR0 and CSPAR1 each have a reset value of one. The reset values of the most significant bits of each field are ...
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The base address field in the boot chip-select base address register CSBARBT has a reset value of all zeros, so that when the initial access to address $000000 is made, an address match occurs, and the CSBOOT signal is asserted. ...
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Access to the port and H data and data direction registers, and the port C, E, and F pin assignment registers require three clock cycles to ensure timing com- patibility with external port replacement logic. ...
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Port E pin assignment register (PEPAR) bits control the function of each port E pin. Any bit set to one defines the corresponding pin bus control signal, with the function shown in Table 5-28. Any bit cleared ...
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IRQ7/PF7 7 IRQ6/PF6 IRQ5/PF5 8 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 FASTREF/PF0 Figure 5-23 Port F Block Diagram Port F pin assignment register (PFPAR) fields determine the functions of pairs of port F pins. Table 5-29 shows port F pin assignments. Table ...
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Table 5-30 PFPAR Pin Functions PFPAx Bits When the corresponding pin is configured for edge detection, a port F edge-detect flag register (PORTFE) bit is set if an edge is detected. PORTFE bits remain set, regard- less of the subsequent ...
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Factory Test The test submodule supports scan-based testing of the various MCU modules in- tegrated into the SCIM2 to support production test. Test submodule registers are in- tended for Motorola use only. Register names and addresses are ...
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MOTOROLA 5-76 MC68HC16Y3/916Y3 USER’S MANUAL ...
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SECTION 6STANDBY RAM MODULE The standby RAM (SRAM) module consists of a fixed-location control register block and an array of fast (two clock) static RAM that may be mapped to a user specified location in the system memory map. The ...
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SRAM Array Address Space Type The RASP[1:0] in RAMMCR determine the SRAM array address space type. The SRAM module can respond to both program and data space accesses or to program space accesses only. Because the CPU16 operates in ...
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When a synchronous reset occurs while a byte or word SRAM access is in progress, the access is completed. If reset occurs during the first word access of a long-word operation, only the first word access is completed. If reset ...
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MOTOROLA 6-4 STANDBY RAM MODULE MC68HC16Y3/916Y3 USER’S MANUAL ...
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SECTION 7MASKED ROM MODULE The masked ROM module (MRM) is used only in the MC68HC16Y3. It consists of two fixed-location control register blocks and a 64-Kbyte and a 32-Kbyte array, for a total of 96 K-bytes of mask-programmed read-only memory ...
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LOCK can be written once only to a value of one. This prevents accidental remapping of the array. 7.3 MRM Array Address Space Type ASPC[1:0] in MRMCR determines ROM array address space type. The module can respond to both program ...
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WAIT[1: Refer to 5.6 Bus Operation for more information concerning access times. 7.5 Low-Power Stop Mode Operation Low-power stop mode minimizes MCU power consumption. Setting the STOP bit in MRMCR places the MRM in low-power stop ...
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MOTOROLA 7-4 MASKED ROM MODULE MC68HC16Y3/916Y3 USER’S MANUAL ...
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SECTION 8FLASH EEPROM MODULE The flash EEPROM modules serve as nonvolatile, fast-access, electrically erasable and programmable ROM-emulation memory. These modules are used only in the MC68HC916Y3. The MC68HC916Y3 contains a 96-Kbyte module. The 96-Kbytes is divided into 16- Kbyte, 32-Kbyte, ...
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Four additional flash EEPROM words in the control block can contain bootstrap infor- mation for use during reset. Control registers are located in supervisor data space. Re- fer to D.5 Flash EEPROM Modulefor register and bit field information. The control ...
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If the state of the STOP shadow bit is zero, and bus pin DATA14 is pulled high during reset, the STOP bit in the FEExMCR is cleared during reset. The array responds nor- mally to the bootstrap address range and ...
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The following paragraphs give step-by-step procedures for programming and erasure of flash EEPROM arrays. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for information on programming and erasing specifications for the flash EEPROM module. 8.3.5 Programming The following steps are used to ...
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INCREASE V PROGRAM/ERASE/VERIFY LEVEL CLEAR n COUNTER, pp CLEAR MARGIN FLAG SET LAT, CLEAR ERAS WRITE DATA TO ADDRESS SET ENPE START PROGRAM PULSE TIMER (pw DELAY FOR pw CLEAR ENPE, START t pr DELAY FOR t MARGIN FLAG SET ...
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Erasure The following steps are used to erase a flash EEPROM array. Figure 8 flowchart of the erasure operation. Refer to Figures A-36 and A-37 in APPENDIX A ELECTRI- CAL CHARACTERISTICS for V 1. Increase voltage applied ...
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REDUCE V FPE TO PROGRAM/ERASE/VERIFY LEVEL CLEAR n CLEAR MARGIN FLAG SET LAT, SET ERAS WRITE TO ARRAY OR CONTROL BLOCK SET ENPE START ERASE PULSE TIMER (t DELAY FOR t CLEAR ENPE, START t DELAY FOR t MARGIN FLAG ...
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MOTOROLA 8-8 FLASH EEPROM MODULE MC68HC16Y3/916Y3 USER’S MANUAL ...