MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 473

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

DIV2 — Divide by 2 Control
SOFT RST — Soft Reset
ETBANK[1:0] — Entry Table Bank Select
FPSCK[2:0] — Filter Prescaler Clock
MC68HC16Y3/916Y3
USER’S MANUAL
When asserted, the DIV2 bit, along with the TCR1P bit and the PSCK bit in the TPUM-
CR, determines the rate of the TCR1 counter in the TPU2. If set, the TCR1 counter
increments at a rate of two system clocks. If negated, TCR1 increments at the rate de-
termined by control bits in the TCR1P and PSCK fields.
The TPU2 performs an internal reset when both the SOFT RST bit in the TPUMCR2
and the STOP bit in TPUMCR are set. The CPU16 must write zero to the SOFT RST
bit to bring the TPU2 out of reset. The SOFT RST bit must be asserted for at least nine
clocks.
The entry table bank (ETBANK[1:0]) field determines the bank where the microcoded
entry table is situated. After reset, this field is %00. This control bit field is write once
after reset. ETBANK[1:0] is used when the microcode contains entry tables not located
in the default bank 0. To execute the ROM functions on this MCU, ETBANK[1:0] must
be 00. Refer to Table D-60.
The filter prescaler clock control bit field determines the ratio between system clock
frequency and minimum detectable pulses. The reset value of these bits is zero,
defining the filter clock as four system clocks. Refer to Table D-61.
0 = TCR1 increments at rate determined by control bits in the TCR1P and PSCK
1 = Causes TCR1 counter to increment at a rate of the system clock divided by two.
0 = Normal operation
1 = Puts TPU2 in reset until bit is cleared
fields of the TPUMCR register.
Do not attempt to access any other TPU2 registers when this bit is
asserted. When this bit is asserted, it is the only accessible bit in the
register.
This field should not be modified by the programmer unless neces-
sary because of custom microcode.
Table D-60 Entry Table Bank Location
ETBANK
00
01
10
11
NOTE
NOTE
BANK
0
1
2
3
MOTOROLA
D-95