MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 303

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.8.3.1 Output Compare 1
13.8.3.2 Forced Output Compare
13.9 Input Capture 4/Output Compare 5
13.10 Pulse Accumulator
MC68HC16Y3/916Y3
USER’S MANUAL
Output compare 1 can affect any or all of OC[5:1] when an output match occurs. In
addition to allowing generation of multiple control signals from a single comparison op-
eration, this function makes it possible for two or more output compare functions to
control the state of a single OC pin. Output pulses as short as one timer count can be
generated in this way.
The OC1 action mask register (OC1M) and the OC1 action data register (OC1D) con-
trol OC1 function. Setting a bit in OC1M selects a corresponding bit in the GPT parallel
data port. Bits in OC1D determine whether selected bits are to be set or cleared when
an OC1 match occurs. Pins must be configured as outputs in order for the data in the
register to be driven out on the corresponding pin. If an OC1 match and another output
match occur at the same time and both attempt to alter the same pin, the OC1 function
controls the state of the pin.
Timer compare force register (CFORC) is used to make forced compares. The action
taken as a result of a forced compare is the same as when an output compare match
occurs, except that status flags are not set. Forced channels take programmed actions
immediately after the write to CFORC.
The CFORC register is implemented as the upper byte of a 16-bit register which also
contains the PWM control register C (PWMC). It can be accessed as eight bits or a
word access can be used. Reads of force compare bits (FOC) have no meaning and
always return zeros. These bits are self-negating.
The IC4/OC5 pin can be used for input capture, output compare, or general-purpose
I/O. A function enable bit (I4/O5) in the pulse accumulator control register (PACTL)
configures the pin for input capture (IC4) or output compare function (OC5). Both bits
are cleared during reset, configuring the pin as an input, but also enabling the OC5
function. IC4/OC5 I/O functions are controlled by DDGP7 in the port GP data direction
register (DDRGP).
The 16-bit register (TI4/O5) used with the IC4/OC5 function acts as an input capture
register or as an output compare register depending on which function is selected.
When used as the input capture 4 register, it cannot be written to except in test or
freeze mode.
The pulse accumulator counter (PACNT) is an 8-bit read/write up-counter. PACNT can
operate in external event counting or gated time accumulation modes. Figure 13-5 is
a block diagram of the pulse accumulator.
GENERAL-PURPOSE TIMER
MOTOROLA
13-15