MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 139

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6.3 Fast Termination Cycles
MC68HC16Y3/916Y3
USER’S MANUAL
When an external device can meet fast access timing, an internal chip-select circuit
fast termination option can provide a two-cycle external bus transfer. Because the
chip-select circuits are driven from the system clock, the bus cycle termination is in-
herently synchronized with the system clock.
If multiple chip-selects are to be used to provide control signals to a single device and
match conditions occur simultaneously, all MODE, STRB, and associated DSACK
fields must be programmed to the same value. This prevents a conflict on the internal
bus when the wait states are loaded into the DSACK counter shared by all chip-
selects.
1) NEGATE DS AND AS
2) REMOVE DATA FROM DATA BUS
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
ASSERT DS AND WAIT FOR DSACK (S3)
TERMINATE OUTPUT TRANSFER (S5)
PLACE DATA ON DATA[15:0] (S2)
OPTIONAL STATE (S4)
ADDRESS DEVICE (S0)
START NEXT CYCLE
ASSERT AS (S1)
NO CHANGE
MCU
Figure 5-12 Write Cycle Flowchart
1) DECODE ADDRESS
2) LATCH DATA FROM DATA BUS
3) ASSERT DSACK SIGNALS
ACCEPT DATA (S2 + S3)
TERMINATE CYCLE
NEGATE DSACK
PERIPHERAL
MOTOROLA
WR CYC FLOW
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