MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 480

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

ERAS — Erase Control
LAT — Latch Control
D-102
MOTOROLA
Entire Array
NOTES:
This bit invokes a special program-verify circuit. During programming sequences
(ERAS = 0), VFPE is used in conjunction with the LAT bit to determine when program-
ming of a location is complete. If VFPE and LAT are both set, a bit-wise exclusive-OR
of the latched data with the data in the location being programmed occurs when any
valid TPUFLASH location is read. If the location is completely programmed, a value of
zero is read. Any other value indicates that the location is not fully programmed. When
VFPE is cleared, normal reads of valid TPUFLASH locations occur.
The ERAS bit in BFECTL configures the TPUFLASH array for programming or era-
sure. Setting ERAS causes all locations in the array and all TPUFLASH shadow bits
in the control block to be configured for erasure. Table 14-7 shows the address ranges
that must be written to during an erase operation in order to erase specific blocks of
the TPUFLASH array.
When the LAT bit is set, ERAS also determines whether a read returns the value of
the addressed location (ERAS = 1) or the location being programmed (ERAS = 0).
The value of ERAS cannot be changed if the program/erase voltage is turned on
(ENPE = 1).
Block
1. The TPUFLASH base address high and low registers (TFBAH and TFBAL) specify ADDR[23:11] of the block
2. These address bits are “don’t cares” when specifying the block to be erased.
3. Erasing the entire array also erases the TPUFLASH control register shadow bits.
0
1
2
3
4
5
6
7
to be erased.
0 = TPUFLASH configured for programming.
1 = TPUFLASH configured for erasure.
0 = Programming latches disabled.
1 = Programming latches enabled.
3
Reserved
Addresses Affected
Table 14-7 TPUFLASH Erase Operation Address Ranges
$0000 - $007F
$0100 - $017F
$0180 - $01FF
$0200 - $02FF
$0300 - $03FF
$0400 - $05FF
$0600 - $07FF
$0600 - $07FF
$0080 - $0100
TFBAH/TFBAL
ADDR[23:11]
Address Bits Used to Specify Block for Erasure
1
ADDR[10:6]
X
2
A5
1
1
1
1
1
1
1
1
1
0
A4
X
X
0
0
0
0
1
1
1
0
A3
X
X
0
0
1
1
0
0
1
1
MC68HC16Y3/916Y3
USER’S MANUAL
A2
X
X
0
1
0
1
0
1
0
1
A1
X
2
A0
X
2