MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 212

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.5.1 Low-Power Stop Mode
10.5.2 Freeze Mode
10.6 Analog Subsystem
10-4
MOTOROLA
When the STOP bit in ADCMCR is set, the IMB clock signal to the ADC is disabled.
This places the module in an idle state, and power consumption is minimized. The
ABIU does not shut down and ADC registers are still accessible. If a conversion is in
progress when STOP is set, it is aborted.
STOP is set during system reset, and must be cleared before the ADC can be used.
Because analog circuit bias currents are turned off during low-power stop mode, the
ADC requires recovery time after STOP is cleared.
Execution of the CPU16 LPSTOP command places the entire modular microcontroller
in low-power stop mode. Refer to 5.3.4 Low-Power Operation for more information.
When the CPU16 in the modular microcontroller enters background debugging mode,
the FREEZE signal is asserted. The type of response is determined by the value of the
FRZ[1:0] field in the ADCMCR. Table 10-1 shows the different ADC responses to
FREEZE assertion.
When the ADC freezes, the ADC clock stops and all sequential activity ceases. Con-
tents of control and status registers remain valid while frozen. When the FREEZE sig-
nal is negated, ADC activity resumes.
If the ADC freezes during a conversion, activity resumes with the next step in the con-
version sequence. However, capacitors in the analog conversion circuitry discharge
while the ADC is frozen; as a result, the conversion will be inaccurate.
Refer to 4.14.4 Background Debug Mode for more information.
The analog subsystem consists of a multiplexer, sample capacitors, a buffer amplifier,
an RC DAC array, and a high-gain comparator. Comparator output sequences the
successive approximation register (SAR). The interface between the comparator and
the SAR is the boundary between ADC analog and digital subsystems.
FRZ[1:0]
Table 10-1 FRZ Field Selection
ANALOG-TO-DIGITAL CONVERTER
00
01
10
11
Finish conversion, then freeze
Freeze immediately
Ignore FREEZE
Response
Reserved
MC68HC16Y3/916Y3
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