MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 180

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.10.3 Port F
5-72
MOTOROLA
Port E pin assignment register (PEPAR) bits control the function of each port E pin.
Any bit set to one defines the corresponding pin to be a bus control signal, with the
function shown in Table 5-28. Any bit cleared to zero defines the corresponding pin to
be an I/O pin, controlled by PORTE and DDRE.
BERR and DATA8 control the state of this register following reset. If BERR and/or
DATA8 are low during reset, this register is set to $00, defining all port E pins as I/O
pins. If BERR and DATA8 are both high during reset, the register is set to $FF, which
defines all port E pins as bus control signals.
Port F consists of eight I/O pins, a data register, a data direction register, a pin assign-
ment register, an edge-detect flag register, an edge-detect interrupt vector register, an
edge-detect interrupt level register, and associated control logic. Figure 5-23 is a
block diagram of port F pins, registers, and control logic.
Port F pins can be configured as interrupt request inputs, edge-detect input/outputs,
or discrete input/outputs. When port F pins are configured for edge detection, and a
priority level is specified by writing a value to the port F edge-detect interrupt level
register (PFLVR), port F control logic generates an interrupt request when the
specified edge is detected. Interrupt vector assignment is made by writing a value to
the port F edge-detect interrupt vector register (PFIVR). The edge-detect interrupt has
the lowest arbitration priority in the SCIM2.
A write to the port F data register (PORTF) is stored in the internal data latch, and if
any port F pin is configured as an output, the value stored for that bit is driven on the
pin. A read of PORTF returns the value on a pin only if the pin is configured as a dis-
crete input. Otherwise, the value read is the value stored in the data register. PORTF
is a single register that can be accessed in two locations (PORTF1, PORTF0). It can
be read or written at any time, including when the MCU is in emulator mode.
Port F data direction register (DDRF) bits control the direction of port F pin drivers
when the pins are configured for I/O. Setting any bit in this register configures the
corresponding pin as an output. Clearing any bit in this register configures the
corresponding pin as an input.
PEPAR Bit
PEPA7
PEPA6
PEPA5
PEPA4
PEPA1
PEPA0
Table 5-28 Port E Pin Assignments
Port E Signal
PE7
PE6
PE5
PE4
PE1
PE0
Bus Control Signal
DSACK0
DSACK1
SIZ1
SIZ0
AS
DS
MC68HC16Y3/916Y3
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