MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 178

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MC68HC916Y3CFT16

Manufacturer Part Number
MC68HC916Y3CFT16
Description
IC MCU 96K FLASH 16MHZ 160-QFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet

Specifications of MC68HC916Y3CFT16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
5.10 General Purpose Input/Output
5-70
MOTOROLA
The base address field in the boot chip-select base address register CSBARBT has a
reset value of all zeros, so that when the initial access to address $000000 is made,
an address match occurs, and the CSBOOT signal is asserted. The block size field in
CSBARBT has a reset value of 512 Kbytes. Table 5-26 shows CSBOOT reset values.
The SCIM2 contains six general-purpose input/output ports: ports A, B, E, F, G, and
H. (Port C, an output-only port, is included under the discussion of chip-selects). Ports
A, B, and G are available in single-chip mode only and port H is available in single-chip
or 8-bit expanded modes only. Ports E, F, G, and H have an associated data direction
register to configure each pin as input or output. Ports A and B share a data direction
register that configures each port as input or output. Ports E and F have associated
pin assignment registers that configure each pin as digital I/O or an alternate function.
Port F has an edge-detect flag register that indicates whether a transition has occurred
on any of its pins.
Table 5-27 shows the shared functions of the general-purpose I/O ports and the
modes in which they are available.
Table 5-26 CSBOOT Base and Option Register Reset Values
Port
G
H
A
B
E
F
NOTES:
Table 5-27 General-Purpose I/O Ports
Async/sync mode
Upper/lower byte
1. These fields are not used unless “Address space” is
Address space
Base address
set to CPU space.
Read/write
Autovector
Block size
DSACK
AS/DS
Fields
IPL
IRQ[7:1]/FASTREF
Shared Function
1
ADDR[18:11]
ADDR[10:3]
Bus Control
DATA[15:8]
DATA[7:0]
Interrupt vector externally
Asynchronous mode
Supervisor space
13 Wait states
Reset Values
Read/write
Both bytes
512 Kbyte
Any level
$000000
AS
Single-chip, 8-Bit expanded
Single-chip
Single-chip
Single-chip
Modes
All
All
MC68HC16Y3/916Y3
USER’S MANUAL

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