MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 126

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5-18
MOTOROLA
Both writes must occur before timeout in the order listed. Any number of instructions
can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the
software watchdog timing (SWT[1:0]) field in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be
selected. The value of SWP is affected by the state of the MODCLK pin during reset,
as shown in Table 5-5. System software can change SWP value.
SWT[1:0] selects the divide ratio used to establish the software watchdog timeout
period.
The following equation calculates the timeout period for a slow reference frequency.
The following equation calculates the timeout period for a fast reference frequency.
The following equation calculates the timeout period for an externally input clock
frequency on both slow and fast reference frequency devices.
Table 5-6 shows the divide ratio for each combination of SWP and SWT[1:0] bits.
When SWT[1:0] are modified, a watchdog service sequence must be performed be-
fore the new timeout period can take effect.
Timeout Period
Timeout Period
Timeout Period
Table 5-5 MODCLK Pin and SWP Bit During Reset
=
0 (External Clock)
1 (Internal Clock)
------------------------------------------------------------------------------------------------------------------------------------------- -
128 Divide Ratio Specified by SWP and SWT[1:0]
=
=
MODCLK
Divide Ratio Specified by SWP and SWT[1:0]
----------------------------------------------------------------------------------------------------------------------- -
Divide Ratio Specified by SWP and SWT[1:0]
----------------------------------------------------------------------------------------------------------------------- -
1 ( 512)
0 ( 1)
SWP
f
f
f
ref
ref
ref
MC68HC16Y3/916Y3
USER’S MANUAL