MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 195

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.3.2 Bootstrap Operation
8.3.3 Normal Operation
8.3.4 Program/Erase Operation
MC68HC16Y3/916Y3
USER’S MANUAL
If the state of the STOP shadow bit is zero, and bus pin DATA14 is pulled high during
reset, the STOP bit in the FEExMCR is cleared during reset. The array responds nor-
mally to the bootstrap address range and the flash EEPROM array base address.
If the STOP shadow bit is one, or the module’s associated data bus pin is pulled low
during reset, the STOP bit in the FEExMCR is set. The flash EEPROM array is dis-
abled until the STOP bit is cleared by software. It will not respond to the bootstrap ad-
dress range, or the flash EEPROM array base address in FEExBAH and FEExBAL,
allowing an external device to respond to the flash EEPROM array's address space or
bootstrap information. Since the erased state of the shadow bits is one, erased flash
EEPROM modules (which include the shadow registers in the control blocks) come
out of reset in STOP mode.
After reset, the CPU begins bootstrap operation by fetching initial values for its internal
registers from special bootstrap word addresses $000000 through $000006. If BOOT
= 0 and STOP = 0 in FEExMCR, the flash EEPROM module is configured to recognize
these addresses after a reset and provide this information from the FEExBS[3:0] boot-
strap registers in the flash EEPROM control block. The information in these registers
is programmed by the user.
The flash EEPROM module allows a byte or aligned-word read in one bus cycle. Long-
word reads require two bus cycles.
The module checks function codes to verify access privileges. All control block ad-
dresses must be in supervisor data space. Array accesses are defined by the state of
ASPC[1:0] in FEExMCR. Access time is governed by the WAIT[1:0] field in FEExMCR.
Accesses to any address in the address block defined by FEExBAH and FEExBAL
which does not fall within the array are ignored, allowing external devices to adjoin
flash EEPROM arrays which do not entirely fill the entire address space specified by
FEExBAH and FEExBAL.
An erased flash bit has a logic state of one. A bit must be programmed to change its
state from one to zero. Erasing a bit returns it to a logic state of one. Programming and
erasing the flash module requires a series of control register writes and a write to an
array address. The same procedure is used to program control registers that contain
flash shadow bits. Programming is restricted to a single byte or aligned word at a time.
The entire array and the shadow register bits are erased at the same time.
When multiple flash modules share a single V
than one flash module at a time. Normal accesses to modules that are not being pro-
grammed are not affected by programming or erasure of another flash module.
FLASH EEPROM MODULE
FPE
pin, do not program or erase more
MOTOROLA
8-3