MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 170

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5-62
MOTOROLA
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Logic can also generate
DSACK and AVEC signals internally. A single DSACK generator is shared by all chip-
selects. Each signal can also be synchronized with the ECLK signal available on
ADDR23.
When a memory access occurs, chip-select logic compares address space type,
address, type of access, transfer size, and interrupt priority (in the case of interrupt
acknowledge) to parameters stored in chip-select registers. If all parameters match,
the appropriate chip-select signal is asserted. Select signals are active low. If a chip-
select function is given the same address as a microcontroller module or an internal
memory array, an access to that address goes to the module or array, and the chip-
select signal is not asserted. The external address and data buses do not reflect the
internal access.
All chip-select circuits are configured for operation out of reset. However, all chip-
select signals except CSBOOT are disabled, and cannot be asserted until the
BYTE[1:0] field in the corresponding option register is programmed to a non-zero val-
ue to select a transfer size. The chip-select option register must not be written until a
base address has been written to a proper base address register. Alternate functions
for chip-select pins are enabled if appropriate data bus pins are held low at the release
of RESET. Refer to 5.7.3.2 Data Bus Mode Selection for more information. Figure 5-
21 is a functional diagram of a single chip-select circuit.
DSACK
BUS CONTROL
AVEC
ADDRESS
INTERNAL
SIGNALS
Figure 5-21 Chip-Select Circuit Block Diagram
GENERATOR
AVEC
BASE ADDRESS REGISTER
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
GENERATOR
DSACK
ASSIGNMENT
REGISTER
PIN
CONTROL
TIMING
AND
REGISTER
DATA
PIN
MC68HC16Y3/916Y3
USER’S MANUAL
PIN
CHIP SEL BLOCK