MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 131

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.5.1 Bus Control Signals
5.5.1.1 Address Bus
5.5.1.2 Address Strobe
5.5.1.3 Data Bus
5.5.1.4 Data Strobe
MC68HC16Y3/916Y3
USER’S MANUAL
The external bus has 24 address lines and 16 data lines. ADDR[19:0] are normal ad-
dress outputs; ADDR[23:20] follow the output state of ADDR19. The EBI provides
dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and
long-word transfers. Port width is the maximum number of bits accepted or provided
by the external memory system during a bus transfer. Widths of eight and sixteen bits
are accessed through the use of asynchronous cycles controlled by the size (SIZ1 and
SIZ0) and data size acknowledge (DSACK1 and DSACK0) pins. Multiple bus cycles
may be required for a dynamically sized transfers.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic
is synchronized with EBI transfers. Refer to 5.9 Chip-Selects for more information.
The address bus provides addressing information to external devices. The data bus
transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals,
one for the address bus and another for the data bus, indicate the validity of an
address and provide timing information for data.
Control signals indicate the beginning of each bus cycle, the address space, the size
of the transfer, and the type of cycle. External devices decode these signals and
respond to transfer data and terminate the bus cycle. The EBI can operate in an
asynchronous mode for any port width.
Bus signals ADDR[19:0] define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MCU places the address on the bus at the
beginning of a bus cycle. The address is valid while AS is asserted.
Address strobe (AS) is a timing signal that indicates the validity of an address on the
address bus and of many control signals.
Signals DATA[15:0] form a bidirectional, non-multiplexed parallel bus that transfers
data to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in
one bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of
the port width or operand size.
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an
external device to place data on the bus. DS is asserted at the same time as AS during
a read cycle. For a write cycle, DS signals an external device that data on the bus is
valid.
MOTOROLA
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