MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 179

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.10.1 Ports A and B
5.10.2 Port E
MC68HC16Y3/916Y3
USER’S MANUAL
Access to the port A, B, E, F, G, and H data and data direction registers, and the port
C, E, and F pin assignment registers require three clock cycles to ensure timing com-
patibility with external port replacement logic. Port registers are byte-addressable and
are grouped to allow coherent word access to port data register pairs A-B and G-H, as
well as word-aligned long word coherency of A-B-G-H port data registers.
If emulation mode is enabled, the emulation mode chip-select signal CSE is asserted
whenever an access to ports A, B, E, G, and H data and data direction registers or the
port E pin assignment register is made. The SCIM2 does not respond to these access-
es, but allows external logic, such as a Motorola port replacement unit (PRU)
MC68HC33 to respond. Port C data and data direction register, port F data and data
direction register, and the port F pin assignment register remain accessible.
A write to the port A, B, E, F, G, or H data register is stored in the internal data latch.
If any port pin is configured as an output, the value stored for that bit is driven on the
pin. A read of the port data register returns the value at the pin only if the pin is config-
ured as a discrete input. Otherwise, the value read is the value stored in the register.
Ports A and B are available in single-chip mode only. One data direction register con-
trols data direction for both ports. Port A and B registers can be read or written at any
time the MCU is not in emulator mode.
Port A/B data direction bits (DDA and DDB) control the direction of the pin drivers for
ports A and B, respectively, when the pins are configured for I/O. Setting DDA or DDB
to one configures all pins in the corresponding port as outputs. Clearing DDA or DDB
to zero configures all pins in the corresponding port as inputs.
Port E can be made available in all operating modes. The state of BERR and DATA8
during reset controls whether the port E pins are used as bus control signals or dis-
crete I/O lines.
If the MCU is in emulator mode, an access of the port E data, data direction, or pin
assignment registers (PORTE, DDRE, PEPAR) is forced to go external. This allows
port replacement logic to be supplied externally, giving an emulator access to the bus
control signals.
The port E data register (PORTE) is a single register that can be accessed in two
locations. It can be read or written at any time the MCU is not in emulator mode.
Port E data direction register (DDRE) bits control the direction of the pin drivers when
the pins are configured as I/O. Any bit in this register set to one configures the
corresponding pin as an output. Any bit in this register cleared to zero configures the
corresponding pin as an input. This register can be read or written at any time the MCU
is not in emulator mode.
MOTOROLA
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