MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 176

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5-68
MOTOROLA
Because address match logic functions only after the EBI transfers an interrupt
acknowledge cycle to the external address bus following IARB contention, chip-select
logic generates DSACK signals only in response to interrupt requests from external
IRQ pins. If an internal module makes an interrupt request of a certain priority, and the
chip-select base address and option registers are programmed to generate DSACK
signals in response to an interrupt acknowledge cycle for that priority level, chip-select
logic does not respond to the interrupt acknowledge cycle, and the internal module
supplies a vector number and generates an internal DSACK signal to terminate the cy-
cle.
Perform the following operations before using a chip select to generate an interrupt
acknowledge signal.
1. Program the base address field to all ones.
2. Program block size to no more than 64 Kbytes, so that the address comparator
3. Set the R/W field to read only. An interrupt acknowledge cycle is performed as
4. Set the BYTE field to lower byte when using a 16-bit port, as the external vector
If an interrupting device does not provide a vector number, an autovector
acknowledge must be produced by generating AVEC internally using the chip-se-
lect option register. This terminates the bus cycle.
checks ADDR[19:16] against the corresponding bits in the base address
register. (The CPU16 places the CPU space bus cycle type on ADDR[19:16].)
a read cycle.
for a 16-bit port is fetched from the lower byte. Set the BYTE field to upper byte
when using an 8-bit port.
Figure 5-22 CPU Space Encoding for Interrupt Acknowledge
ACKNOWLEDGE
On a fully bonded SCIM2 implementation, the user can assert the
AVEC/PE2 pin. The AVEC/PE2 pin is not available on the
MC68HC16Y3/916Y3.
INTERRUPT
FUNCTION
1 1 1
2
CODE
0
23
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CPU SPACE
TYPE FIELD
19
16
NOTE
ADDRESS BUS
LEVEL
MC68HC16Y3/916Y3
0
1
USER’S MANUAL
CPU SPACE IACK TIM