MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 202

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.3 TPUFLASH Array
9.4 TPUFLASH Operation
9.4.1 Reset Operation
9-2
MOTOROLA
Shadow registers are programmed or erased in the same manner as locations in the
TPUFLASH array, using the address of the corresponding control registers. When a
shadow register is programmed, the data is not written to the corresponding control
register. The new data is not copied into the control register until the next reset. The
contents of shadow registers are erased whenever the TPUFLASH array is erased.
Configuration information is specified and programmed independently of the TPU-
FLASH array. After reset, registers in the control block that contain writable bits can
be modified. Writes to these registers do not affect the associated shadow register.
Certain registers are writable only when the LOCK bit in TFMCR is disabled or when
the STOP bit in TFMCR is set. These restrictions are noted in the individual register
descriptions.
The base address registers specify the starting address of the TPUFLASH array while
the TPUFLASH is in IMB mode. A default base address can be programmed into the
base address shadow registers. The array base address must be on an even 4-Kbyte
boundary. Because the states of ADDR[23:20] follow the state of ADDR19, addresses
in the range $080000 to $F7FFFF cannot be accessed by the CPU16. If the TPU-
FLASH array is mapped to these addresses, the system must be reset before the array
can be accessed.
Avoid using a base address value that causes the array to overlap control registers. If
a portion of the array overlaps the EEPROM register block, the registers remain ac-
cessible, but accesses to that portion of the array are ignored. If the array overlaps the
control block of another module, however, those registers may become inaccessible.
If the TPUFLASH array overlaps another memory array (RAM or flash EEPROM),
proper access to one or both arrays may not be possible.
The following paragraphs describe the operation of the TPUFLASH during reset, sys-
tem boot, normal operation, and while it is being programmed or erased.
Reset initializes all TPUFLASH control registers. Some bits have fixed default values,
and some take values that are programmed into the associated TPUFLASH shadow
registers.
If the state of the STOP shadow bit is zero, and data bus pin DATA12 is pulled high
during reset, the STOP bit in TFMCR is cleared during reset, and the module responds
to accesses in the range specified by TFBAH and TFBAL. When the BOOT bit is
cleared, the module also responds to bootstrap vector accesses.
TPU FLASH EEPROM MODULE
MC68HC16Y3/916Y3
USER’S MANUAL