MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 330

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

A-4
MOTOROLA
Num
NOTES:
10. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
1
2
3
4
5
6
1. Tested with either a 4.194 MHz reference or a 32.768 kHz reference.
2. All internal registers retain data at 0 Hz.
3. Assumes that V
4. Assumes that V
5. Cold start is measured from V
6. Internal VCO frequency (f
7. This parameter is periodically sampled rather than 100% tested.
8. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total ex-
9. Proper layout procedures must be followed to achieve specifications.
f
signal. Noise injected into the PLL circuitry via V
crease the J
this parameter should be measured during functional testing of the final system.
oscillator is stable.
stable, followed by V
The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop.
When X = 0, the divider is enabled, and f
When X = 1, the divider is disabled, and f
X must equal one when operating at maximum specified f
ternal resistance from the XFC pin due to external leakage must be greater than 15 M
ification. Filter network geometry can vary depending upon operating environment.
sys
PLL Reference Frequency Range
System Frequency
PLL Lock Time
VCO Frequency
Limp Mode Clock Frequency
CLKOUT Jitter
. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
Slow On-Chip PLL System Frequency
Fast On-Chip PLL System Frequency
External Clock Operation
Changing W or Y in SYNCR or exiting from LPSTOP
Warm Start-up
Cold Start-up (fast reference option only)
SYNCR X bit = 0
SYNCR X bit = 1
Short term (5 s interval)
Long term (500 s interval)
clk
percentage for a given interval. When clock jitter is a critical constraint on control system operation,
1, 7, 8, 9, 10
1, 7, 8 , 9
DDSYN
DDSYN
6
(V
4
2
DD
DD
Characteristic
is stable, that an external filter is attached to the XFC pin, and that the crystal oscillator is
and V
and V
ramp-up. Lock time is measured from V
VCO
DD
Table A-4 Clock Control Timing
DDSYN
DDSYN
) is determined by SYNCR W and Y bit values.
ELECTRICAL CHARACTERISTICS
are stable, that an external filter is attached to the XFC pin, and that the crystal
1
= 5.0 Vdc 10%, V
and V
sys
sys
DD
5
= f
= f
at specified minimum to RESET negated.
VCO
VCO
DDSYN
2.
4.
and V
3
sys
SS
Symbol
.
f
f
= 0 Vdc, T
f
VCO
J
SS
f
t
sys
limp
ref
lpll
clk
DD
and variation in crystal oscillator frequency in-
at specified minimum to RESET negated.
4 (f
A
– 0.05
4 (f
– 0.5
ref
Min
= T
3.2
dc
dc
—
—
—
—
—
—
) /128
ref
L
)
to T
H
2 (f
)
f
MC68HC16Y3/916Y3
sys
f
to guarantee this spec-
sys
16.78
16.78
16.78
16.78
sys
Max
0.05
4.2
0.5
20
50
75
max/2
USER’S MANUAL
max
max)
MHz
MHz
MHz
MHz
Unit
ms