MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 156

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MC68HC916Y3CFT16

Manufacturer Part Number
MC68HC916Y3CFT16
Description
IC MCU 96K FLASH 16MHZ 160-QFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet

Specifications of MC68HC916Y3CFT16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
5.7.3.5 Single-Chip Mode
5.7.3.6 Clock Mode Selection
5-48
MOTOROLA
Single-chip operation is selected when BERR = 0 during reset. BERR can be tied low
permanently to select this configuration. In single-chip configuration, pins DATA[15:0]
are configured as two 8-bit I/O ports, ports G and H. ADDR[18:3] are configured as two
8-bit I/O ports, ports A and B. There is no external data bus path. Expanded mode con-
figuration options are not available: I/O ports A, B, C, E, F, G, and H are always se-
lected. ADDR[2:0] come out of reset in a high-impedance state. After reset, clearing
the ABD bit in SCIMCR enables these pins, and leaving the bit set (its single-chip reset
state) leaves the pins in a disabled (high-impedance) state.
Table 5-19 summarizes SCIM2 pin functions during single-chip operation.
The state of the clock mode (MODCLK) pin during reset determines what clock source
the MCU uses. When MODCLK is held high during reset, the clock signal is generated
from a reference frequency using the clock synthesizer. When MODCLK is held low
during reset, the clock synthesizer is disabled, and an external system clock signal
must be applied. Refer to 5.3 System Clock for more information.
Table 5-19 Single-Chip Mode Reset Configuration
ADDR23/CS10/ECLK
ADDR19/CS6/PC3
ADDR20/CS7/PC4
ADDR21/CS8/PC5
ADDR22/CS9/PC6
IRQ[7:6]/PF[7:6]
Pin(s) Affected
FASTREF/PF0
FC0/CS3/PC0
FC2/CS5/PC2
DSACK0/PE0
DSACK1/PE1
BGACK, CSE
ADDR[18:11]
ADDR[10:3]
DATA[15:8]
DATA[7:0]
SIZ0/PE6
SIZ1/PE7
CSBOOT
FC1/PC1
BG/CSM
BR/CS0
DS/PE4
AS/PE5
CSBOOT 16-Bit
PE[7:4], [1:0]
Function
BGACK
PA[7:0]
PB[7:0]
PC[6:0]
PG[7:0]
PH[7:0]
PF[7:6]
CS0
PF0
BG
MC68HC16Y3/916Y3
USER’S MANUAL

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