MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 138

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6.2.1 Read Cycle
5.6.2.2 Write Cycle
5-30
MOTOROLA
During a read cycle, the MCU transfers data from an external memory or peripheral
device. If the instruction specifies a long-word or word operation, the MCU attempts to
read two bytes at once. For a byte operation, the MCU reads one byte. The portion of
the data bus from which each byte is read depends on operand size, peripheral ad-
dress, and peripheral port size. Figure 5-11 is a flow chart of a word read cycle. Refer
to 5.5.2 Dynamic Bus Sizing, 5.5.4 Misaligned Operands, and the SCIM Reference
Manual (SCIMRM/AD) for more information.
During a write cycle, the MCU transfers data to an external memory or peripheral
device. If the instruction specifies a long-word or word operation, the MCU attempts to
write two bytes at once. For a byte operation, the MCU writes one byte. The portion of
the data bus upon which each byte is written depends on operand size, peripheral ad-
dress, and peripheral port size.
Refer to 5.5.2 Dynamic Bus Sizing and 5.5.4 Misaligned Operands for more informa-
tion. Figure 5-12 is a flow chart of a write-cycle operation for a word transfer. Refer to
the SCIM Reference Manual (SCIMRM/AD) for more information.
1) SET R/W TO READ
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
NEGATE AS AND DS (S5)
ASSERT AS AND DS (S1)
START NEXT CYCLE (S0)
ADDRESS DEVICE (S0)
DECODE DSACK (S3)
LATCH DATA (S4)
Figure 5-11 Word Read Cycle Flowchart
MCU
1) DECODE ADDR, R/W, SIZ[1:0], DS
2) PLACE DATA ON DATA[15:0] OR
3) DRIVE DSACK SIGNALS
1) REMOVE DATA FROM DATA BUS
2) NEGATE DSACK
DATA[15:8] IF 8-BIT DATA
TERMINATE CYCLE (S5)
PRESENT DATA (S2)
PERIPHERAL
MC68HC16Y3/916Y3
USER’S MANUAL
RD CYC FLOW