MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 406

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

BOOT— Boot ROM Control
LOCK — Lock Registers
EMUL — Emulation Mode Control
ASPC[1:0] — ROM Array Space
WAIT[1:0] — Wait States Field
D-28
MOTOROLA
Reset state of BOOT is specified at mask time. This is a read-only bit.
Bootstrap operation is overridden if STOP = 1 at reset.
The reset state of LOCK is specified at mask time. If the reset state of the LOCK is
zero, it can be set once after reset to allow protection of the registers after initialization.
Once the LOCK bit is set, it cannot be cleared again until after a reset. LOCK protects
the ASPC and WAIT fields, as well as the ROMBAL and ROMBAH registers. ASPC,
ROMBAL and ROMBAH are also protected by the STOP bit.
Because the MC68HC16Y3/916Y3 does not support ROM emulation mode, this bit
should never be set.
The ASPC field limits access to the SRAM array in microcontrollers that support
separate user and supervisor operating modes. ASPC1 has no effect because the
CPU16 operates in supervisor mode only. This bit may be read or written at any time.
The reset state of ASPC[1:0] is specified at mask time. Table D-21 shows ASPC[1:0]
encoding.
WAIT[1:0] specifies the number of wait states inserted by the MRM during ROM array
accesses. The reset state of WAIT[1:0] is user specified. The field can be written only
if LOCK = 0 and STOP = 1. Table D-22 shows the wait states field.
0 = ROM responds to bootstrap word locations during reset vector fetch.
1 = ROM does not respond to bootstrap word locations during reset vector fetch.
0 = Write lock disabled. Protected registers and fields can be written.
1 = Write lock enabled. Protected registers and fields cannot be written.
0 = Normal ROM operation
1 = Accesses to the ROM array are forced external, allowing memory selected by
the CSM pin to respond to the access.
WAIT[1:0]
00
01
10
11
Table D-21 ROM Array Space Field
ASPC[1:0]
Table D-22 Wait States Field
X0
X1
Wait States
Number of
REGISTER SUMMARY
–1
0
1
2
Program and data accesses
Program access only
State Specified
Clocks per Transfer
3
4
5
2
MC68HC16Y3/916Y3
USER’S MANUAL