MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 142

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6.4.2 LPSTOP Broadcast Cycle
5-34
MOTOROLA
BREAKPOINT OPERATION FLOW
Low-power stop mode is initiated by the CPU16. Individual modules can be stopped
by setting the STOP bits in each module configuration register. The SCIM2 can turn
off system clocks after execution of the LPSTOP instruction. When the CPU16 exe-
cutes LPSTOP, the LPSTOP broadcast cycle is generated. The SCIM2 brings the
MCU out of low-power mode when either an interrupt of higher priority than the inter-
rupt mask level in the CPU16 condition code register or a reset occurs. Refer to 5.3.4
Low-Power Operation and SECTION 4 CENTRAL PROCESSOR UNIT for more in-
formation.
During an LPSTOP broadcast cycle, the CPU16 performs a CPU space write to ad-
dress $3FFFE. This write puts a copy of the interrupt mask value in the clock control
logic. The mask is encoded on the data bus as shown in Figure 5-15.
The LPSTOP CPU space cycle is shown externally (if the bus is available) as an indi-
cation to external devices that the MCU is going into low-power stop mode. The SCIM2
provides an internally generated DSACK response to this cycle. The timing of this bus
cycle is the same as for a fast termination write cycle. If the bus is not available (arbi-
trated away), the LPSTOP broadcast cycle is not shown externally.
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE ALL ONES ON ADDR[4:2]
5) SET ADDR1 TO ONE
6) SET SIZE TO WORD
7) ASSERT AS AND DS
INITIATE HARDWARE BREAKPOINT PROCESSING
ACKNOWLEDGE BREAKPOINT
NEGATE DSACK or BERR
NEGATE AS or DS
CPU16
Figure 5-14 Breakpoint Operation Flowchart
ASSERT DSACK OR BERR TO INITIATE EXCEPTION PROCESSING
PERIPHERAL
CPU16 BREAKPOINT OPERATION FLOW
MC68HC16Y3/916Y3
USER’S MANUAL