MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 469

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PCBK — PC Breakpoint Flag
CHBK — Channel Register Breakpoint Flag
SRBK — Service Request Breakpoint Flag
TPUF — TPU2 FREEZE Flag
D.10.5 TPU2 Interrupt Configuration Register
TICR — TPU2 Interrupt Configuration Register
CIRL[2:0] — Channel Interrupt Request Level
CIBV[3:0] — Channel Interrupt Base Vector
D.10.6 Channel Interrupt Enable Register
CIER — Channel Interrupt Enable Register
CH[15:0] — Channel Interrupt Enable/Disable
MC68HC16Y3/916Y3
USER’S MANUAL
CH 15
15
15
0
RESET:
RESET:
PCBK is asserted if a breakpoint occurs because of a PC (microprogram counter)
register match with the PC breakpoint register. PCBK is negated when the BKPT flag
is cleared.
CHBK is asserted if a breakpoint occurs because of a CHAN register match with the
CHAN register breakpoint register. CHBK is negated when the BKPT flag is cleared.
SRBK is asserted if a breakpoint occurs because of any of the service request latches
being asserted along with their corresponding enable flag in the development support
control register. SRBK is negated when the BKPT flag is cleared.
TPUF is set whenever the TPU2 is in a halted state as a result of FREEZE being as-
serted. This flag is automatically negated when the TPU2 exits the halted state be-
cause of FREEZE being negated.
This three-bit field specifies the interrupt request level for all channels. Level seven for
this field indicates a non-maskable interrupt; level zero indicates that all channel inter-
rupts are disabled.
The TPU2 is assigned 16 unique interrupt vector numbers, one vector number for each
channel. The CIBV field specifies the most significant nibble of all 16 TPU2 channel
interrupt vector numbers. The lower nibble of the TPU2 interrupt vector number is de-
termined by the channel number on which the interrupt occurs.
CH 14
0 = Channel interrupts disabled
1 = Channel interrupts enabled
14
0
NOT USED
CH 13
13
0
CH 12
12
0
CH 11
11
0
CH 10
10
10
0
0
CIRL[2:0]
CH 9
9
0
9
0
CH 8
8
0
8
0
CH 7
7
0
7
0
CH 6
6
0
6
0
CIBV[3:0]
CH 5
5
0
5
0
CH 4
4
0
4
0
CH 3
3
3
0
CH 2
NOT USED
2
0
$YFFE0A
$YFFE08
MOTOROLA
CH 1
1
0
CH 0
D-91
0
0
0