MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 417

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PADA[7:0] — Port ADA Data Pins
D.6.4 ADC Control Register 0
ADCTL0 — ADC Control Register 0
RES10 — 10-Bit Resolution
STS[1:0] — Sample Time Selection
PRS[4:0] — Prescaler Rate Selection
MC68HC16Y3/916Y3
USER’S MANUAL
15
RESET:
A read of PADA[7:0] returns the logic level of the port ADA pins. If an input is not at an
appropriate logic level (that is, outside the defined levels), the read is indeterminate.
Use of a port ADA pin for digital input does not preclude its simultaneous use as an
analog input.
ADCTL0 is used to select 8- or 10-bit conversions, sample time, and ADC clock
frequency. Writes to it have immediate effect.
Conversion results are appropriately aligned in result registers to reflect the number of
bits.
Total conversion time is the sum of initial sample time, transfer time, final sample time,
and resolution time. Initial sample time is fixed at two ADC clocks. Transfer time is
fixed at two ADC clocks. Resolution time is fixed at 10 ADC clocks for an 8-bit conver-
sion and 12 ADC clocks for a 10-bit conversion. Final sample time is determined by
the STS[1:0] field. Refer to Table D-29.
The ADC clock is derived from the system clock by a programmable prescaler. ADC
clock period is determined by the value of the PRS field in ADCTL0. The prescaler has
two stages. The first stage is a 5-bit modulus counter. It divides the system clock by
any value from 2 to 32 (PRS[4:0] = %00000 to %11111). The second stage is a divide-
by-two circuit. Refer to Table D-30.
0 = 8-bit conversion
1 = 10-bit conversion
14
13
12
NOT USED
STS[1:0]
11
Table D-29 Sample Time Selection
00
01
10
11
10
9
8
RES10
16 ADC Clock Periods
2 ADC Clock Periods
4 ADC Clock Periods
8 ADC Clock Periods
7
0
Sample Time
6
0
STS[1:0]
5
0
4
0
3
0
PRS[4:0]
2
0
$YFF70A
MOTOROLA
1
1
D-39
0
1