D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 781

MCU 3V 0K 100-TQFP

D13007VX13V

Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of D13007VX13V

Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an
external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. However, when PA
PB
low. Clock pin P6
3
are used as CS output pins, they go to the high-impedance state at the same time as RES goes
P6
RES
Internal reset
signal
A
CS
AS, RD
(read)
HWR, LWR
(write)
D
(write)
I/O port,
PA
A
20
21
15
7
4
0
, CS
/A
to A
to D
23
7
0
0
to PA
to CS
7
Figure D.2 Reset during Memory Access (Modes 3 and 4)
/φ goes to the output state at the next rise of φ after RES goes low.
6
1
/
4
to PA
Access to external
T1
6
are used as address bus pins, or when P8
0
memory
go high, and D
T2
T3
Rev.5.00 Sep. 12, 2007 Page 751 of 764
15
to D
0
go to the high-impedance state.
High impedance
High impedance
H'000000
Appendix D Pin States
REJ09B0396-0500
3
to P8
1
and PB
0
to

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