D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 119
D13007VX13V
Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13007VX13V
Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Bit 2⎯Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit 2
IPRB2
0
1
Bit 1⎯Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests.
Bit 1
IPRB1
0
1
Bit 0⎯Reserved: This bit can be written and read, but it does not affect interrupt priority.
5.2.3
ISR is an 8-bit readable/writable register that indicates the status of IRQ
requests.
Bit
Initial value
Read/Write
Note:
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6⎯Reserved: These bits can not be modified and are always read as 0.
*
Only 0 can be written, to clear flags.
IRQ Status Register (ISR)
Description
SCI channel 1 interrupt requests have priority level 0 (low priority)
SCI channel 1 interrupt requests have priority level 1 (high priority)
Description
SCI channel 2 interrupt requests have priority level 0 (low priority)
SCI channel 2 interrupt requests have priority level 1 (high priority)
Reserved bits
⎯
⎯
7
0
⎯
⎯
6
0
IRQ5F
R/(W) *
5
0
IRQ4F
R/(W) *
4
0
IRQ to IRQ flags
These bits indicate IRQ to IRQ
interrupt request status
IRQ3F
R/(W) *
Rev.5.00 Sep. 12, 2007 Page 89 of 764
3
0
5
IRQ2F
R/(W) *
0
2
0
0
to IRQ
5. Interrupt Controller
IRQ1F
R/(W) *
5
1
0
REJ09B0396-0500
5
interrupt
(Initial value)
(Initial value)
IRQ0F
R/(W) *
0
0
0
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