D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 426

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11. Programmable Timing Pattern Controller (TPC)
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5
and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits
7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFFA5
Bit
Initial value
Read/Write
Address H'FFFA7
Bit
Initial value
Read/Write
11.2.6
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP
specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The
address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output
trigger or different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Rev.5.00 Sep. 12, 2007 Page 396 of 764
REJ09B0396-0500
Next Data Register B (NDRB)
15
NDR7
R/W
to TP
⎯
⎯
7
0
7
1
8
). During TPC output, when an 16-bit timer compare match event
NDR6
Reserved bits
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
⎯
⎯
6
0
6
1
NDR5
R/W
⎯
⎯
5
0
5
1
NDR4
R/W
⎯
⎯
4
0
4
1
NDR3
R/W
⎯
⎯
3
1
3
0
Next data 3 to 0
These bits store the next output
data for TPC output group 0
NDR2
Reserved bits
R/W
⎯
⎯
2
1
2
0
NDR1
R/W
⎯
⎯
1
1
1
0
NDR0
R/W
⎯
⎯
0
1
0
0