D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 498

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface
Rev.5.00 Sep. 12, 2007 Page 468 of 764
REJ09B0396-0500
Clear DR bit to 0 and set DDR to 1
Write transmit data in TDR
and set MPBT bit in SSR
Clear TE bit to 0 in SCR
Read TDRE flag in SSR
Read TEND flag in SSR
Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
Output break signal?
All data transmitted?
Clear TDRE flag to 0
Start transmitting
TDRE = 1
TEND = 1
Initialize
<End>
Yes
Yes
Yes
Yes
No
No
No
No
(4)
(1)
(2)
(3)
(1)
(2)
(3)
(4)
SCI initialization:
the transmit data output function of the TxD pin
is selected automatically.
SCI status check and transmit data write:
read SSR, check that the TDRE flag is 1, then
write transmit data in TDR. Also set the MPBT
flag to 0 or 1 in SSR. Finally, clear the TDRE
flag to 0.
To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written, write data
in TDR, then clear the TDRE flag to 0. When
the DMAC is activated by a transmit-data-
empty interrupt request (TXI) to write data in
TDR, the TDRE flag is checked and cleared
automatically.
To output a break signal at the end of serial
transmission:
set the DDR bit to 1 and clear the DR bit to 0
(DDR and DR are I/O port registers), then
clear the TE bit to 0 in SCR.